Commit 593f4a78 authored by Maciej W. Rozycki's avatar Maciej W. Rozycki Committed by Ingo Molnar
Browse files

x86: APIC: remove apic_write_around(); use alternatives 



Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time.  Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum.  Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends.  The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.

I had the feeling no one else was brave enough to do it, so I went ahead
and here it is.  Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.

I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out.  The option will get removed from them at
the next run.

Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.

Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 5b664cb2

arch/x86/Kconfig.cpu

+0 −4
Original line number Diff line number Diff line
@@ -362,10 +362,6 @@ config X86_ALIGNMENT_16 
	def_bool y

	depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || X86_ELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1



config X86_GOOD_APIC

	def_bool y

	depends on MK7 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || MK8 || MEFFICEON || MCORE2 || MVIAC7 || X86_64



config X86_INTEL_USERCOPY

	def_bool y

	depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2

arch/x86/kernel/apic_32.c

+36 −39
Original line number Diff line number Diff line
@@ -177,7 +177,7 @@ void __cpuinit enable_NMI_through_LVT0(void) 
	/* Level triggered for 82489DX */

	if (!lapic_is_integrated())

		v |= APIC_LVT_LEVEL_TRIGGER;

	apic_write_around(APIC_LVT0, v);

	apic_write(APIC_LVT0, v);

}



/**
@@ -212,9 +212,6 @@ int lapic_get_maxlvt(void) 
 * this function twice on the boot CPU, once with a bogus timeout

 * value, second time for real. The other (noncalibrating) CPUs

 * call this function only once, with the real, calibrated value.

 *

 * We do reads before writes even if unnecessary, to get around the

 * P5 APIC double write bug.

 */

static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)

{
@@ -229,18 +226,18 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 
	if (!irqen)

		lvtt_value |= APIC_LVT_MASKED;



	apic_write_around(APIC_LVTT, lvtt_value);

	apic_write(APIC_LVTT, lvtt_value);



	/*

	 * Divide PICLK by 16

	 */

	tmp_value = apic_read(APIC_TDCR);

	apic_write_around(APIC_TDCR, (tmp_value

				& ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))

				| APIC_TDR_DIV_16);

	apic_write(APIC_TDCR,

		   (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |

		   APIC_TDR_DIV_16);



	if (!oneshot)

		apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);

		apic_write(APIC_TMICT, clocks / APIC_DIVISOR);

}



/*
@@ -249,7 +246,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 
static int lapic_next_event(unsigned long delta,

			    struct clock_event_device *evt)

{

	apic_write_around(APIC_TMICT, delta);

	apic_write(APIC_TMICT, delta);

	return 0;

}
@@ -278,7 +275,7 @@ static void lapic_timer_setup(enum clock_event_mode mode, 
	case CLOCK_EVT_MODE_SHUTDOWN:

		v = apic_read(APIC_LVTT);

		v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);

		apic_write_around(APIC_LVTT, v);

		apic_write(APIC_LVTT, v);

		break;

	case CLOCK_EVT_MODE_RESUME:

		/* Nothing to do here */
@@ -693,44 +690,44 @@ void clear_local_APIC(void) 
	 */

	if (maxlvt >= 3) {

		v = ERROR_APIC_VECTOR; /* any non-zero vector will do */

		apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);

		apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);

	}

	/*

	 * Careful: we have to set masks only first to deassert

	 * any level-triggered sources.

	 */

	v = apic_read(APIC_LVTT);

	apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);

	apic_write(APIC_LVTT, v | APIC_LVT_MASKED);

	v = apic_read(APIC_LVT0);

	apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);

	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);

	v = apic_read(APIC_LVT1);

	apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);

	apic_write(APIC_LVT1, v | APIC_LVT_MASKED);

	if (maxlvt >= 4) {

		v = apic_read(APIC_LVTPC);

		apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);

		apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);

	}



	/* lets not touch this if we didn't frob it */

#ifdef CONFIG_X86_MCE_P4THERMAL

	if (maxlvt >= 5) {

		v = apic_read(APIC_LVTTHMR);

		apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);

		apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);

	}

#endif

	/*

	 * Clean APIC state for other OSs:

	 */

	apic_write_around(APIC_LVTT, APIC_LVT_MASKED);

	apic_write_around(APIC_LVT0, APIC_LVT_MASKED);

	apic_write_around(APIC_LVT1, APIC_LVT_MASKED);

	apic_write(APIC_LVTT, APIC_LVT_MASKED);

	apic_write(APIC_LVT0, APIC_LVT_MASKED);

	apic_write(APIC_LVT1, APIC_LVT_MASKED);

	if (maxlvt >= 3)

		apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);

		apic_write(APIC_LVTERR, APIC_LVT_MASKED);

	if (maxlvt >= 4)

		apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);

		apic_write(APIC_LVTPC, APIC_LVT_MASKED);



#ifdef CONFIG_X86_MCE_P4THERMAL

	if (maxlvt >= 5)

		apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);

		apic_write(APIC_LVTTHMR, APIC_LVT_MASKED);

#endif

	/* Integrated APIC (!82489DX) ? */

	if (lapic_is_integrated()) {
@@ -756,7 +753,7 @@ void disable_local_APIC(void) 
	 */

	value = apic_read(APIC_SPIV);

	value &= ~APIC_SPIV_APIC_ENABLED;

	apic_write_around(APIC_SPIV, value);

	apic_write(APIC_SPIV, value);



	/*

	 * When LAPIC was disabled by the BIOS and enabled by the kernel,
@@ -865,8 +862,8 @@ void __init sync_Arb_IDs(void) 
	apic_wait_icr_idle();



	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");

	apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG

				| APIC_DM_INIT);

	apic_write(APIC_ICR,

		   APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | APIC_DM_INIT);

}



/*
@@ -902,16 +899,16 @@ void __init init_bsp_APIC(void) 
	else

		value |= APIC_SPIV_FOCUS_DISABLED;

	value |= SPURIOUS_APIC_VECTOR;

	apic_write_around(APIC_SPIV, value);

	apic_write(APIC_SPIV, value);



	/*

	 * Set up the virtual wire mode.

	 */

	apic_write_around(APIC_LVT0, APIC_DM_EXTINT);

	apic_write(APIC_LVT0, APIC_DM_EXTINT);

	value = APIC_DM_NMI;

	if (!lapic_is_integrated())		/* 82489DX */

		value |= APIC_LVT_LEVEL_TRIGGER;

	apic_write_around(APIC_LVT1, value);

	apic_write(APIC_LVT1, value);

}



static void __cpuinit lapic_setup_esr(void)
@@ -926,7 +923,7 @@ static void __cpuinit lapic_setup_esr(void) 


		/* enables sending errors */

		value = ERROR_APIC_VECTOR;

		apic_write_around(APIC_LVTERR, value);

		apic_write(APIC_LVTERR, value);

		/*

		 * spec says clear errors after enabling vector.

		 */
@@ -989,7 +986,7 @@ void __cpuinit setup_local_APIC(void) 
	 */

	value = apic_read(APIC_TASKPRI);

	value &= ~APIC_TPRI_MASK;

	apic_write_around(APIC_TASKPRI, value);

	apic_write(APIC_TASKPRI, value);



	/*

	 * After a crash, we no longer service the interrupts and a pending
@@ -1047,7 +1044,7 @@ void __cpuinit setup_local_APIC(void) 
	 * Set spurious IRQ vector

	 */

	value |= SPURIOUS_APIC_VECTOR;

	apic_write_around(APIC_SPIV, value);

	apic_write(APIC_SPIV, value);



	/*

	 * Set up LVT0, LVT1:
@@ -1069,7 +1066,7 @@ void __cpuinit setup_local_APIC(void) 
		apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",

				smp_processor_id());

	}

	apic_write_around(APIC_LVT0, value);

	apic_write(APIC_LVT0, value);



	/*

	 * only the BP should see the LINT1 NMI signal, obviously.
@@ -1080,7 +1077,7 @@ void __cpuinit setup_local_APIC(void) 
		value = APIC_DM_NMI | APIC_LVT_MASKED;

	if (!integrated)		/* 82489DX */

		value |= APIC_LVT_LEVEL_TRIGGER;

	apic_write_around(APIC_LVT1, value);

	apic_write(APIC_LVT1, value);

}



void __cpuinit end_local_APIC_setup(void)
@@ -1091,7 +1088,7 @@ void __cpuinit end_local_APIC_setup(void) 
	/* Disable the local apic timer */

	value = apic_read(APIC_LVTT);

	value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);

	apic_write_around(APIC_LVTT, value);

	apic_write(APIC_LVTT, value);



	setup_apic_nmi_watchdog(NULL);

	apic_pm_activate();
@@ -1419,7 +1416,7 @@ void disconnect_bsp_APIC(int virt_wire_setup) 
		value &= ~APIC_VECTOR_MASK;

		value |= APIC_SPIV_APIC_ENABLED;

		value |= 0xf;

		apic_write_around(APIC_SPIV, value);

		apic_write(APIC_SPIV, value);



		if (!virt_wire_setup) {

			/*
@@ -1432,10 +1429,10 @@ void disconnect_bsp_APIC(int virt_wire_setup) 
				APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);

			value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;

			value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);

			apic_write_around(APIC_LVT0, value);

			apic_write(APIC_LVT0, value);

		} else {

			/* Disable LVT0 */

			apic_write_around(APIC_LVT0, APIC_LVT_MASKED);

			apic_write(APIC_LVT0, APIC_LVT_MASKED);

		}



		/*
@@ -1449,7 +1446,7 @@ void disconnect_bsp_APIC(int virt_wire_setup) 
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);

		value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;

		value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);

		apic_write_around(APIC_LVT1, value);

		apic_write(APIC_LVT1, value);

	}

}

arch/x86/kernel/cpu/bugs.c

+1 −22
Original line number Diff line number Diff line
@@ -131,12 +131,6 @@ static void __init check_popad(void) 
 *   (for due to lack of "invlpg" and working WP on a i386)

 * - In order to run on anything without a TSC, we need to be

 *   compiled for a i486.

 * - In order to support the local APIC on a buggy Pentium machine,

 *   we need to be compiled with CONFIG_X86_GOOD_APIC disabled,

 *   which happens implicitly if compiled for a Pentium or lower

 *   (unless an advanced selection of CPU features is used) as an

 *   otherwise config implies a properly working local APIC without

 *   the need to do extra reads from the APIC.

 */



static void __init check_config(void)
@@ -151,21 +145,6 @@ static void __init check_config(void) 
	if (boot_cpu_data.x86 == 3)

		panic("Kernel requires i486+ for 'invlpg' and other features");

#endif



/*

 * If we were told we had a good local APIC, check for buggy Pentia,

 * i.e. all B steppings and the C2 stepping of P54C when using their

 * integrated APIC (see 11AP erratum in "Pentium Processor

 * Specification Update").

 */

#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_GOOD_APIC)

	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL

	    && cpu_has_apic

	    && boot_cpu_data.x86 == 5

	    && boot_cpu_data.x86_model == 2

	    && (boot_cpu_data.x86_mask < 6 || boot_cpu_data.x86_mask == 11))

		panic("Kernel compiled for PMMX+, assumes a local APIC without the read-before-write bug!");

#endif

}

arch/x86/kernel/cpu/intel.c

+10 −0
Original line number Diff line number Diff line
@@ -227,6 +227,16 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) 
	if (cpu_has_bts)

		ds_init_intel(c);



	/*

	 * See if we have a good local APIC by checking for buggy Pentia,

	 * i.e. all B steppings and the C2 stepping of P54C when using their

	 * integrated APIC (see 11AP erratum in "Pentium Processor

	 * Specification Update").

	 */

	if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&

	    (c->x86_mask < 0x6 || c->x86_mask == 0xb))

		set_cpu_cap(c, X86_FEATURE_11AP);



#ifdef CONFIG_X86_NUMAQ

	numaq_tsc_disable();

#endif

arch/x86/kernel/cpu/mcheck/p4.c

+2 −2
Original line number Diff line number Diff line
@@ -102,7 +102,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c) 
	/* The temperature transition interrupt handler setup */

	h = THERMAL_APIC_VECTOR;		/* our delivery vector */

	h |= (APIC_DM_FIXED | APIC_LVT_MASKED);	/* we'll mask till we're ready */

	apic_write_around(APIC_LVTTHMR, h);

	apic_write(APIC_LVTTHMR, h);



	rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);

	wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03 , h);
@@ -114,7 +114,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c) 
	wrmsr(MSR_IA32_MISC_ENABLE, l | (1<<3), h);



	l = apic_read(APIC_LVTTHMR);

	apic_write_around(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);

	apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);

	printk(KERN_INFO "CPU%d: Thermal monitoring enabled\n", cpu);



	/* enable thermal throttle processing */

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