Commit 593caa07 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu/psp: update topology info structures



topology info structure needs to match with the one defined
in xgmi ta

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarShaoyun Liu <Shaoyun.Liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4b93151f
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+13 −16
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@
#define PSP_TMR_SIZE	0x400000

struct psp_context;
struct psp_xgmi_node_info;
struct psp_xgmi_topology_info;

enum psp_ring_type
@@ -161,21 +162,17 @@ struct amdgpu_psp_funcs {
					enum AMDGPU_UCODE_ID);
};

struct psp_xgmi_topology_info {
	/* Generated by PSP to identify the GPU instance within xgmi connection */
#define AMDGPU_XGMI_MAX_CONNECTED_NODES		64
struct psp_xgmi_node_info {
	uint64_t				node_id;
	/*
	 * If all bits set to 0 , driver indicates it wants to retrieve the xgmi
	 * connection vector topology, but not access enable the connections
	 * if some or all bits are set to 1, driver indicates it want to retrieve the
	 * current xgmi topology and  access enable the link to GPU[i] associated
	 * with the bit position in the  vector.
	 * On return,: bits indicated which xgmi links are present/active depending
	 * on the  value passed in. The relative bit offset for the  relative GPU index
	 * within the  hive is always marked active.
	 */
	uint32_t			connection_mask;
	uint32_t			reserved; /* must be  0 */
	uint8_t					num_hops;
	uint8_t					is_sharing_enabled;
	enum ta_xgmi_assigned_sdma_engine	sdma_engine;
};

struct psp_xgmi_topology_info {
	uint32_t			num_nodes;
	struct psp_xgmi_node_info	nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
};

#define psp_prep_cmd_buf(ucode, type) (psp)->funcs->prep_cmd_buf((ucode), (type))
+5 −7
Original line number Diff line number Diff line
@@ -63,7 +63,7 @@ static struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)

int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
{
	struct psp_xgmi_topology_info tmp_topology[AMDGPU_MAX_XGMI_DEVICE_PER_HIVE];
	struct psp_xgmi_topology_info tmp_topology;
	struct amdgpu_hive_info *hive;
	struct amdgpu_xgmi	*entry;
	struct amdgpu_device 	*tmp_adev;
@@ -76,7 +76,7 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
	adev->gmc.xgmi.node_id = psp_xgmi_get_node_id(&adev->psp);
	adev->gmc.xgmi.hive_id = psp_xgmi_get_hive_id(&adev->psp);

	memset(&tmp_topology[0], 0, sizeof(tmp_topology));
	memset(&tmp_topology, 0, sizeof(tmp_topology));
	mutex_lock(&xgmi_mutex);
	hive = amdgpu_get_xgmi_hive(adev);
	if (!hive)
@@ -84,9 +84,9 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)

	list_add_tail(&adev->gmc.xgmi.head, &hive->device_list);
	list_for_each_entry(entry, &hive->device_list, head)
		tmp_topology[count++].node_id = entry->node_id;
		tmp_topology.nodes[count++].node_id = entry->node_id;

	ret = psp_xgmi_get_topology_info(&adev->psp, count, tmp_topology);
	ret = psp_xgmi_get_topology_info(&adev->psp, count, &tmp_topology);
	if (ret) {
		dev_err(adev->dev,
			"XGMI: Get topology failure on device %llx, hive %llx, ret %d",
@@ -96,7 +96,7 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
	}
	/* Each psp need to set the latest topology */
	list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
		ret = psp_xgmi_set_topology_info(&tmp_adev->psp, count, tmp_topology);
		ret = psp_xgmi_set_topology_info(&tmp_adev->psp, count, &tmp_topology);
		if (ret) {
			dev_err(tmp_adev->dev,
				"XGMI: Set topology failure on device %llx, hive %llx, ret %d",
@@ -115,5 +115,3 @@ exit:
	mutex_unlock(&xgmi_mutex);
	return ret;
}