PCI: Always set prefetchable base/limit upper32 registers (59353ea3) · Commits · 戴 / test

Prior to we always initialized the upper 32bits of the prefetchable memory window, regardless of the address range used. Now we only touch it for a >32bit address, which means the upper32 registers remain whatever the BIOS initialized them too. It's valid for the BIOS to set the upper32 base/limit to 0xffffffff/0x00000000, which makes us program prefetchable ranges like 0xffffffffabc00000 - 0x00000000abc00000 Revert the chunk of that made this conditional so we always write the upper32 registers and remove now unused pref_mem64 variable. Signed-off-by:

Alex Williamson <alex.williamson@hp.com> Signed-off-by:

Jesse Barnes <jbarnes@virtuousgeek.org>

drivers/pci/setup-bus.c

+3 −8

Original line number	Diff line number	Diff line
		@@ -140,7 +140,6 @@ static void pci_setup_bridge(struct pci_bus *bus)
		struct resource *res;
		struct pci_bus_region region;
		u32 l, bu, lu, io_upper16;
		int pref_mem64;

		if (pci_is_enabled(bridge))
		return;
		@@ -194,7 +193,6 @@ static void pci_setup_bridge(struct pci_bus *bus)
		pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);

		/* Set up PREF base/limit. */
		pref_mem64 = 0;
		bu = lu = 0;
		res = bus->resource[2];
		pcibios_resource_to_bus(bridge, &region, res);
		@@ -202,7 +200,6 @@ static void pci_setup_bridge(struct pci_bus *bus)
		l = (region.start >> 16) & 0xfff0;
		l \|= region.end & 0xfff00000;
		if (res->flags & IORESOURCE_MEM_64) {
		pref_mem64 = 1;
		bu = upper_32_bits(region.start);
		lu = upper_32_bits(region.end);
		}
		@@ -214,11 +211,9 @@ static void pci_setup_bridge(struct pci_bus *bus)
		}
		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);

		if (pref_mem64) {
		/* Set the upper 32 bits of PREF base & limit. */
		pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
		pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
		}

		pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
		}

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