Commit 59245ce0 authored by Tero Kristo's avatar Tero Kristo
Browse files

clk: ti: move OMAP4+ DPLL implementation under drivers/clk 



With the legacy clock support gone, the OMAP4 specific DPLL implementations
can be moved under the clock driver. Change some of the function prototypes
to be static at the same time, and remove some exports from the global TI
clock driver header.

Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
parent b138b028

arch/arm/mach-omap2/Makefile

+3 −3
Original line number Diff line number Diff line
@@ -193,12 +193,12 @@ obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o 
obj-$(CONFIG_ARCH_OMAP3)		+= dpll3xxx.o

obj-$(CONFIG_ARCH_OMAP3)		+= clkt_iclk.o

obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common)

obj-$(CONFIG_ARCH_OMAP4)		+= dpll3xxx.o dpll44xx.o

obj-$(CONFIG_ARCH_OMAP4)		+= dpll3xxx.o

obj-$(CONFIG_SOC_AM33XX)		+= $(clock-common) dpll3xxx.o

obj-$(CONFIG_SOC_OMAP5)			+= $(clock-common)

obj-$(CONFIG_SOC_OMAP5)			+= dpll3xxx.o dpll44xx.o

obj-$(CONFIG_SOC_OMAP5)			+= dpll3xxx.o

obj-$(CONFIG_SOC_DRA7XX)		+= $(clock-common)

obj-$(CONFIG_SOC_DRA7XX)		+= dpll3xxx.o dpll44xx.o

obj-$(CONFIG_SOC_DRA7XX)		+= dpll3xxx.o

obj-$(CONFIG_SOC_AM43XX)		+= $(clock-common) dpll3xxx.o



# OMAP2 clock rate set data (old "OPP" data)

arch/arm/mach-omap2/clock.h

+0 −4
Original line number Diff line number Diff line
@@ -183,8 +183,6 @@ struct clksel { 
u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);

void omap3_dpll_allow_idle(struct clk_hw_omap *clk);

void omap3_dpll_deny_idle(struct clk_hw_omap *clk);

void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);

void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);



void __init omap2_clk_disable_clkdm_control(void);
@@ -204,8 +202,6 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val); 
extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);

extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);



unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);



void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,

				   void __iomem **other_reg,

				   u8 *other_bit);

drivers/clk/ti/Makefile

+3 −3
Original line number Diff line number Diff line
@@ -7,10 +7,10 @@ obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-816x.o 
obj-$(CONFIG_ARCH_OMAP2)		+= $(clk-common) interface.o clk-2xxx.o

obj-$(CONFIG_ARCH_OMAP3)		+= $(clk-common) interface.o \

					   clk-3xxx.o

obj-$(CONFIG_ARCH_OMAP4)		+= $(clk-common) clk-44xx.o

obj-$(CONFIG_SOC_OMAP5)			+= $(clk-common) clk-54xx.o

obj-$(CONFIG_ARCH_OMAP4)		+= $(clk-common) clk-44xx.o dpll44xx.o

obj-$(CONFIG_SOC_OMAP5)			+= $(clk-common) clk-54xx.o dpll44xx.o

obj-$(CONFIG_SOC_DRA7XX)		+= $(clk-common) clk-7xx.o \

					   clk-dra7-atl.o

					   clk-dra7-atl.o dpll44xx.o

obj-$(CONFIG_SOC_AM43XX)		+= $(clk-common) clk-43xx.o



ifdef CONFIG_ATAGS

drivers/clk/ti/clock.h

+14 −0
Original line number Diff line number Diff line
@@ -169,6 +169,20 @@ void ti_clk_patch_legacy_clks(struct ti_clk **patch); 
struct clk *ti_clk_register_clk(struct ti_clk *setup);

int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);



extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;



u8 omap2_init_dpll_parent(struct clk_hw *hw);



unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,

					 unsigned long parent_rate);

long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,

				    unsigned long target_rate,

				    unsigned long *parent_rate);

long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,

					unsigned long rate,

					unsigned long min_rate,

					unsigned long max_rate,

					unsigned long *best_parent_rate,

					struct clk_hw **best_parent_clk);



#endif

arch/arm/mach-omap2/dpll44xx.c→drivers/clk/ti/dpll44xx.c

+12 −11
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include <linux/clk.h>

#include <linux/io.h>

#include <linux/bitops.h>

#include <linux/clk/ti.h>



#include "clock.h"
@@ -29,14 +30,14 @@ 
/*

 * Bitfield declarations

 */

#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK		(1 << 8)

#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK		(1 << 10)

#define OMAP4430_DPLL_REGM4XEN_MASK			(1 << 11)

#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK		BIT(8)

#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK		BIT(10)

#define OMAP4430_DPLL_REGM4XEN_MASK			BIT(11)



/* Static rate multiplier for OMAP4 REGM4XEN clocks */

#define OMAP4430_REGM4XEN_MULT				4



void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)

static void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)

{

	u32 v;

	u32 mask;
@@ -48,13 +49,13 @@ void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) 
			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :

			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;



	v = omap2_clk_readl(clk, clk->clksel_reg);

	v = ti_clk_ll_ops->clk_readl(clk->clksel_reg);

	/* Clear the bit to allow gatectrl */

	v &= ~mask;

	omap2_clk_writel(v, clk, clk->clksel_reg);

	ti_clk_ll_ops->clk_writel(v, clk->clksel_reg);

}



void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)

static void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)

{

	u32 v;

	u32 mask;
@@ -66,10 +67,10 @@ void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) 
			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :

			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;



	v = omap2_clk_readl(clk, clk->clksel_reg);

	v = ti_clk_ll_ops->clk_readl(clk->clksel_reg);

	/* Set the bit to deny gatectrl */

	v |= mask;

	omap2_clk_writel(v, clk, clk->clksel_reg);

	ti_clk_ll_ops->clk_writel(v, clk->clksel_reg);

}



const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
@@ -127,7 +128,7 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, 
	rate = omap2_get_dpll_rate(clk);



	/* regm4xen adds a multiplier of 4 to DPLL calculations */

	v = omap2_clk_readl(clk, dd->control_reg);

	v = ti_clk_ll_ops->clk_readl(dd->control_reg);

	if (v & OMAP4430_DPLL_REGM4XEN_MASK)

		rate *= OMAP4430_REGM4XEN_MULT;

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