Commit 58e8ed2e authored by Laurent Pinchart's avatar Laurent Pinchart Committed by Simon Horman
Browse files

arm64: dts: renesas: Convert to new LVDS DT bindings 



The internal LVDS encoder now has DT bindings separate from the DU. Port
the r8a7795 and r8a7796 device trees over to the new model.

Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent dc7a6bab

arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts

+1 −2
Original line number Diff line number Diff line
@@ -40,12 +40,11 @@ 
		 <&cpg CPG_MOD 723>,

		 <&cpg CPG_MOD 722>,

		 <&cpg CPG_MOD 721>,

		 <&cpg CPG_MOD 727>,

		 <&versaclock5 1>,

		 <&x21_clk>,

		 <&x22_clk>,

		 <&versaclock5 2>;

	clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",

	clock-names = "du.0", "du.1", "du.2", "du.3",

		      "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";

};

arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts

+1 −2
Original line number Diff line number Diff line
@@ -41,11 +41,10 @@ 
		 <&cpg CPG_MOD 723>,

		 <&cpg CPG_MOD 722>,

		 <&cpg CPG_MOD 721>,

		 <&cpg CPG_MOD 727>,

		 <&versaclock5 1>,

		 <&versaclock5 3>,

		 <&versaclock5 4>,

		 <&versaclock5 2>;

	clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",

	clock-names = "du.0", "du.1", "du.2", "du.3",

		      "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";

};

arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts

+1 −2
Original line number Diff line number Diff line
@@ -40,12 +40,11 @@ 
		 <&cpg CPG_MOD 723>,

		 <&cpg CPG_MOD 722>,

		 <&cpg CPG_MOD 721>,

		 <&cpg CPG_MOD 727>,

		 <&versaclock5 1>,

		 <&x21_clk>,

		 <&x22_clk>,

		 <&versaclock5 2>;

	clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",

	clock-names = "du.0", "du.1", "du.2", "du.3",

		      "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";

};

arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts

+1 −2
Original line number Diff line number Diff line
@@ -40,12 +40,11 @@ 
		 <&cpg CPG_MOD 723>,

		 <&cpg CPG_MOD 722>,

		 <&cpg CPG_MOD 721>,

		 <&cpg CPG_MOD 727>,

		 <&versaclock6 1>,

		 <&x21_clk>,

		 <&x22_clk>,

		 <&versaclock6 2>;

	clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",

	clock-names = "du.0", "du.1", "du.2", "du.3",

		      "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";

};

arch/arm64/boot/dts/renesas/r8a7795.dtsi

+30 −6
Original line number Diff line number Diff line
@@ -2782,9 +2782,7 @@ 


		du: display@feb00000 {

			compatible = "renesas,du-r8a7795";

			reg = <0 0xfeb00000 0 0x80000>,

			      <0 0xfeb90000 0 0x14>;

			reg-names = "du", "lvds.0";

			reg = <0 0xfeb00000 0 0x80000>;

			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
@@ -2792,9 +2790,8 @@ 
			clocks = <&cpg CPG_MOD 724>,

				 <&cpg CPG_MOD 723>,

				 <&cpg CPG_MOD 722>,

				 <&cpg CPG_MOD 721>,

				 <&cpg CPG_MOD 727>;

			clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";

				 <&cpg CPG_MOD 721>;

			clock-names = "du.0", "du.1", "du.2", "du.3";

			vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>;

			status = "disabled";
@@ -2822,6 +2819,33 @@ 
				port@3 {

					reg = <3>;

					du_out_lvds0: endpoint {

						remote-endpoint = <&lvds0_in>;

					};

				};

			};

		};



		lvds0: lvds@feb90000 {

			compatible = "renesas,r8a7795-lvds";

			reg = <0 0xfeb90000 0 0x14>;

			clocks = <&cpg CPG_MOD 727>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 727>;

			status = "disabled";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

					lvds0_in: endpoint {

						remote-endpoint = <&du_out_lvds0>;

					};

				};

				port@1 {

					reg = <1>;

					lvds0_out: endpoint {

					};

				};

			};

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