Commit 58e508b6 authored by Alex Sierra's avatar Alex Sierra Committed by Alex Deucher
Browse files

drm/amdgpu: implement tlbs invalidate on gfx9 gfx10 



tlbs invalidate pointer function added to kiq_pm4_funcs struct.
This way, tlb flush can be done through kiq member.
TLBs invalidatation implemented for gfx9 and gfx10.

Signed-off-by: default avatarAlex Sierra <alex.sierra@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f167ea6a

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

+4 −0
Original line number Diff line number Diff line
@@ -76,11 +76,15 @@ struct kiq_pm4_funcs { 
					struct amdgpu_ring *ring,

					u64 addr,

					u64 seq);

	void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring,

				uint16_t pasid, uint32_t flush_type,

				bool all_hub);

	/* Packet sizes */

	int set_resources_size;

	int map_queues_size;

	int unmap_queues_size;

	int query_status_size;

	int invalidate_tlbs_size;

};



struct amdgpu_kiq {

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+15 −0
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ 
#include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"



#include "soc15.h"

#include "soc15d.h"

#include "soc15_common.h"

#include "clearstate_gfx10.h"

#include "v10_structs.h"
@@ -345,15 +346,29 @@ static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 
	amdgpu_ring_write(kiq_ring, upper_32_bits(seq));

}



static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,

				uint16_t pasid, uint32_t flush_type,

				bool all_hub)

{

	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));

	amdgpu_ring_write(kiq_ring,

			PACKET3_INVALIDATE_TLBS_DST_SEL(1) |

			PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |

			PACKET3_INVALIDATE_TLBS_PASID(pasid) |

			PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));

}



static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {

	.kiq_set_resources = gfx10_kiq_set_resources,

	.kiq_map_queues = gfx10_kiq_map_queues,

	.kiq_unmap_queues = gfx10_kiq_unmap_queues,

	.kiq_query_status = gfx10_kiq_query_status,

	.kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,

	.set_resources_size = 8,

	.map_queues_size = 7,

	.unmap_queues_size = 6,

	.query_status_size = 7,

	.invalidate_tlbs_size = 12,

};



static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+14 −0
Original line number Diff line number Diff line
@@ -837,15 +837,29 @@ static void gfx_v9_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 
	amdgpu_ring_write(kiq_ring, upper_32_bits(seq));

}



static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,

				uint16_t pasid, uint32_t flush_type,

				bool all_hub)

{

	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));

	amdgpu_ring_write(kiq_ring,

			PACKET3_INVALIDATE_TLBS_DST_SEL(1) |

			PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |

			PACKET3_INVALIDATE_TLBS_PASID(pasid) |

			PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));

}



static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = {

	.kiq_set_resources = gfx_v9_0_kiq_set_resources,

	.kiq_map_queues = gfx_v9_0_kiq_map_queues,

	.kiq_unmap_queues = gfx_v9_0_kiq_unmap_queues,

	.kiq_query_status = gfx_v9_0_kiq_query_status,

	.kiq_invalidate_tlbs = gfx_v9_0_kiq_invalidate_tlbs,

	.set_resources_size = 8,

	.map_queues_size = 7,

	.unmap_queues_size = 6,

	.query_status_size = 7,

	.invalidate_tlbs_size = 12,

};



static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)

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