riscv: move flush_icache_{all,mm} to cacheflush.c (58de7754) · Commits · 戴 / test

arch/riscv/include/asm/cacheflush.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -47,7 +47,7 @@ static inline void flush_dcache_page(struct page *page)

		#else /* CONFIG_SMP */

		#define flush_icache_all() sbi_remote_fence_i(NULL)
		void flush_icache_all(void);
		void flush_icache_mm(struct mm_struct *mm, bool local);

		#endif /* CONFIG_SMP */

arch/riscv/kernel/smp.c

+0 −49

Original line number	Diff line number	Diff line
		@@ -205,52 +205,3 @@ void smp_send_reschedule(int cpu)
		send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
		}

		/*
		* Performs an icache flush for the given MM context. RISC-V has no direct
		* mechanism for instruction cache shoot downs, so instead we send an IPI that
		* informs the remote harts they need to flush their local instruction caches.
		* To avoid pathologically slow behavior in a common case (a bunch of
		* single-hart processes on a many-hart machine, ie 'make -j') we avoid the
		* IPIs for harts that are not currently executing a MM context and instead
		* schedule a deferred local instruction cache flush to be performed before
		* execution resumes on each hart.
		*/
		void flush_icache_mm(struct mm_struct *mm, bool local)
		{
		unsigned int cpu;
		cpumask_t others, hmask, *mask;

		preempt_disable();

		/* Mark every hart's icache as needing a flush for this MM. */
		mask = &mm->context.icache_stale_mask;
		cpumask_setall(mask);
		/* Flush this hart's I$ now, and mark it as flushed. */
		cpu = smp_processor_id();
		cpumask_clear_cpu(cpu, mask);
		local_flush_icache_all();

		/*
		* Flush the I$ of other harts concurrently executing, and mark them as
		* flushed.
		*/
		cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
		local \|= cpumask_empty(&others);
		if (mm != current->active_mm \|\| !local) {
		cpumask_clear(&hmask);
		riscv_cpuid_to_hartid_mask(&others, &hmask);
		sbi_remote_fence_i(hmask.bits);
		} else {
		/*
		* It's assumed that at least one strongly ordered operation is
		* performed on this hart between setting a hart's cpumask bit
		* and scheduling this MM context on that hart. Sending an SBI
		* remote message will do this, but in the case where no
		* messages are sent we still need to order this hart's writes
		* with flush_icache_deferred().
		*/
		smp_mb();
		}

		preempt_enable();
		}

arch/riscv/mm/cacheflush.c

+61 −0

Original line number	Diff line number	Diff line
		@@ -14,6 +14,67 @@
		#include <asm/pgtable.h>
		#include <asm/cacheflush.h>

		#ifdef CONFIG_SMP

		#include <asm/sbi.h>

		void flush_icache_all(void)
		{
		sbi_remote_fence_i(NULL);
		}

		/*
		* Performs an icache flush for the given MM context. RISC-V has no direct
		* mechanism for instruction cache shoot downs, so instead we send an IPI that
		* informs the remote harts they need to flush their local instruction caches.
		* To avoid pathologically slow behavior in a common case (a bunch of
		* single-hart processes on a many-hart machine, ie 'make -j') we avoid the
		* IPIs for harts that are not currently executing a MM context and instead
		* schedule a deferred local instruction cache flush to be performed before
		* execution resumes on each hart.
		*/
		void flush_icache_mm(struct mm_struct *mm, bool local)
		{
		unsigned int cpu;
		cpumask_t others, hmask, *mask;

		preempt_disable();

		/* Mark every hart's icache as needing a flush for this MM. */
		mask = &mm->context.icache_stale_mask;
		cpumask_setall(mask);
		/* Flush this hart's I$ now, and mark it as flushed. */
		cpu = smp_processor_id();
		cpumask_clear_cpu(cpu, mask);
		local_flush_icache_all();

		/*
		* Flush the I$ of other harts concurrently executing, and mark them as
		* flushed.
		*/
		cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
		local \|= cpumask_empty(&others);
		if (mm != current->active_mm \|\| !local) {
		cpumask_clear(&hmask);
		riscv_cpuid_to_hartid_mask(&others, &hmask);
		sbi_remote_fence_i(hmask.bits);
		} else {
		/*
		* It's assumed that at least one strongly ordered operation is
		* performed on this hart between setting a hart's cpumask bit
		* and scheduling this MM context on that hart. Sending an SBI
		* remote message will do this, but in the case where no
		* messages are sent we still need to order this hart's writes
		* with flush_icache_deferred().
		*/
		smp_mb();
		}

		preempt_enable();
		}

		#endif /* CONFIG_SMP */

		void flush_icache_pte(pte_t pte)
		{
		struct page *page = pte_page(pte);

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