ARM: dts: r8a7794: Convert to new CPG/MSSR bindings (58d6c357) · Commits · 戴 / test

Convert the R-Car E2 SoC from the old "Renesas R-Car Gen2 Clock Pulse Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop (MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT bindings. This simplifies the DTS files, and allows to add support for reset control later. Signed-off-by:

Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:

Simon Horman <horms+renesas@verge.net.au>

arch/arm/boot/dts/r8a7794-alt.dts

+1 −2

Original line number	Diff line number	Diff line
		@@ -167,8 +167,7 @@
		pinctrl-names = "default";
		status = "okay";

		clocks = <&mstp7_clks R8A7794_CLK_DU0>,
		<&mstp7_clks R8A7794_CLK_DU1>,
		clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
		<&x13_clk>, <&x2_clk>;
		clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";

arch/arm/boot/dts/r8a7794-silk.dts

+1 −2

Original line number	Diff line number	Diff line
		@@ -423,8 +423,7 @@
		pinctrl-names = "default";
		status = "okay";

		clocks = <&mstp7_clks R8A7794_CLK_DU0>,
		<&mstp7_clks R8A7794_CLK_DU1>,
		clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
		<&x2_clk>, <&x3_clk>;
		clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";

arch/arm/boot/dts/r8a7794.dtsi

+80 −448

File changed.

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