Commit 586ec5dc authored by Samson Tam's avatar Samson Tam Committed by Alex Deucher
Browse files

drm/amd/display: do not force UCLK DPM to stay at highest state during display off in DCN2 



[Why]
Add optimization to allow pstate change support when all displays
are off in DCN2.

[How]
Add clk_mgr_helper_get_active_plane_cnt() to sum plane_count for all
valid stream_status[].  If plane_count is 0, then there are no active
or virtual streams present. Use plane_count == 0 as extra condition to
enable p_state_change_support in dcn2_update_clocks().

Signed-off-by: default avatarSamson Tam <Samson.Tam@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5ea23931

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

+19 −0
Original line number Diff line number Diff line
@@ -63,6 +63,25 @@ int clk_mgr_helper_get_active_display_cnt( 
	return display_count;

}



int clk_mgr_helper_get_active_plane_cnt(

		struct dc *dc,

		struct dc_state *context)

{

	int i, total_plane_count;



	total_plane_count = 0;

	for (i = 0; i < context->stream_count; i++) {

		const struct dc_stream_status stream_status = context->stream_status[i];



		/*

		 * Sum up plane_count for all streams ( active and virtual ).

		 */

		total_plane_count += stream_status.plane_count;

	}



	return total_plane_count;

}



void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)

{

	struct dc_link *edp_link = get_edp_link(dc);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

+6 −2
Original line number Diff line number Diff line
@@ -158,6 +158,8 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, 
	bool dpp_clock_lowered = false;

	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

	bool force_reset = false;

	bool p_state_change_support;

	int total_plane_count;



	if (dc->work_arounds.skip_clock_update)

		return;
@@ -213,9 +215,11 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, 
			pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000);

	}



	if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {

	total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);

	p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);

	if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {

		clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;

		clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support;

		clk_mgr_base->clks.p_state_change_support = p_state_change_support;

		if (pp_smu && pp_smu->set_pstate_handshake_support)

			pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support);

	}

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

+4 −0
Original line number Diff line number Diff line
@@ -296,6 +296,10 @@ int clk_mgr_helper_get_active_display_cnt( 
		struct dc *dc,

		struct dc_state *context);



int clk_mgr_helper_get_active_plane_cnt(

		struct dc *dc,

		struct dc_state *context);







#endif //__DAL_CLK_MGR_INTERNAL_H__

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