Commit 58657d18 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branch 'clk-hw-register' (early part) into clk-next 

* 'clk-hw-register' (early part):
  clk: fixed-rate: Add hw based registration APIs
  clk: gpio: Add hw based registration APIs
  clk: composite: Add hw based registration APIs
  clk: fractional-divider: Add hw based registration APIs
  clk: fixed-factor: Add hw based registration APIs
  clk: mux: Add hw based registration APIs
  clk: gate: Add hw based registration APIs
  clk: divider: Add hw based registration APIs
  clkdev: Add clk_hw based registration APIs
  clk: Add clk_hw OF clk providers
  clk: Add {devm_}clk_hw_{register,unregister}() APIs
  clkdev: Remove clk_register_clkdevs()
parents e9471c4e 26ef56be

Documentation/driver-model/devres.txt

+1 −0
Original line number Diff line number Diff line
@@ -236,6 +236,7 @@ certainly invest a bit more effort into libata core layer). 
CLOCK

  devm_clk_get()

  devm_clk_put()

  devm_clk_hw_register()



DMA

  dmam_alloc_coherent()

drivers/clk/clk-composite.c

+33 −12
Original line number Diff line number Diff line
@@ -211,17 +211,18 @@ static void clk_composite_disable(struct clk_hw *hw) 
	gate_ops->disable(gate_hw);

}



struct clk *clk_register_composite(struct device *dev, const char *name,

struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,

			const char * const *parent_names, int num_parents,

			struct clk_hw *mux_hw, const struct clk_ops *mux_ops,

			struct clk_hw *rate_hw, const struct clk_ops *rate_ops,

			struct clk_hw *gate_hw, const struct clk_ops *gate_ops,

			unsigned long flags)

{

	struct clk *clk;

	struct clk_hw *hw;

	struct clk_init_data init;

	struct clk_composite *composite;

	struct clk_ops *clk_composite_ops;

	int ret;



	composite = kzalloc(sizeof(*composite), GFP_KERNEL);

	if (!composite)
@@ -231,12 +232,13 @@ struct clk *clk_register_composite(struct device *dev, const char *name, 
	init.flags = flags | CLK_IS_BASIC;

	init.parent_names = parent_names;

	init.num_parents = num_parents;

	hw = &composite->hw;



	clk_composite_ops = &composite->ops;



	if (mux_hw && mux_ops) {

		if (!mux_ops->get_parent) {

			clk = ERR_PTR(-EINVAL);

			hw = ERR_PTR(-EINVAL);

			goto err;

		}
@@ -251,7 +253,7 @@ struct clk *clk_register_composite(struct device *dev, const char *name, 


	if (rate_hw && rate_ops) {

		if (!rate_ops->recalc_rate) {

			clk = ERR_PTR(-EINVAL);

			hw = ERR_PTR(-EINVAL);

			goto err;

		}

		clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
@@ -286,7 +288,7 @@ struct clk *clk_register_composite(struct device *dev, const char *name, 
	if (gate_hw && gate_ops) {

		if (!gate_ops->is_enabled || !gate_ops->enable ||

		    !gate_ops->disable) {

			clk = ERR_PTR(-EINVAL);

			hw = ERR_PTR(-EINVAL);

			goto err;

		}
@@ -300,24 +302,43 @@ struct clk *clk_register_composite(struct device *dev, const char *name, 
	init.ops = clk_composite_ops;

	composite->hw.init = &init;



	clk = clk_register(dev, &composite->hw);

	if (IS_ERR(clk))

	ret = clk_hw_register(dev, hw);

	if (ret) {

		hw = ERR_PTR(ret);

		goto err;

	}



	if (composite->mux_hw)

		composite->mux_hw->clk = clk;

		composite->mux_hw->clk = hw->clk;



	if (composite->rate_hw)

		composite->rate_hw->clk = clk;

		composite->rate_hw->clk = hw->clk;



	if (composite->gate_hw)

		composite->gate_hw->clk = clk;

		composite->gate_hw->clk = hw->clk;



	return clk;

	return hw;



err:

	kfree(composite);

	return clk;

	return hw;

}



struct clk *clk_register_composite(struct device *dev, const char *name,

			const char * const *parent_names, int num_parents,

			struct clk_hw *mux_hw, const struct clk_ops *mux_ops,

			struct clk_hw *rate_hw, const struct clk_ops *rate_ops,

			struct clk_hw *gate_hw, const struct clk_ops *gate_ops,

			unsigned long flags)

{

	struct clk_hw *hw;



	hw = clk_hw_register_composite(dev, name, parent_names, num_parents,

			mux_hw, mux_ops, rate_hw, rate_ops, gate_hw, gate_ops,

			flags);

	if (IS_ERR(hw))

		return ERR_CAST(hw);

	return hw->clk;

}



void clk_unregister_composite(struct clk *clk)

drivers/clk/clk-divider.c

+83 −8
Original line number Diff line number Diff line
@@ -426,15 +426,16 @@ const struct clk_ops clk_divider_ro_ops = { 
};

EXPORT_SYMBOL_GPL(clk_divider_ro_ops);



static struct clk *_register_divider(struct device *dev, const char *name,

static struct clk_hw *_register_divider(struct device *dev, const char *name,

		const char *parent_name, unsigned long flags,

		void __iomem *reg, u8 shift, u8 width,

		u8 clk_divider_flags, const struct clk_div_table *table,

		spinlock_t *lock)

{

	struct clk_divider *div;

	struct clk *clk;

	struct clk_hw *hw;

	struct clk_init_data init;

	int ret;



	if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {

		if (width + shift > 16) {
@@ -467,12 +468,14 @@ static struct clk *_register_divider(struct device *dev, const char *name, 
	div->table = table;



	/* register the clock */

	clk = clk_register(dev, &div->hw);



	if (IS_ERR(clk))

	hw = &div->hw;

	ret = clk_hw_register(dev, hw);

	if (ret) {

		kfree(div);

		hw = ERR_PTR(ret);

	}



	return clk;

	return hw;

}



/**
@@ -492,11 +495,38 @@ struct clk *clk_register_divider(struct device *dev, const char *name, 
		void __iomem *reg, u8 shift, u8 width,

		u8 clk_divider_flags, spinlock_t *lock)

{

	return _register_divider(dev, name, parent_name, flags, reg, shift,

	struct clk_hw *hw;



	hw =  _register_divider(dev, name, parent_name, flags, reg, shift,

			width, clk_divider_flags, NULL, lock);

	if (IS_ERR(hw))

		return ERR_CAST(hw);

	return hw->clk;

}

EXPORT_SYMBOL_GPL(clk_register_divider);



/**

 * clk_hw_register_divider - register a divider clock with the clock framework

 * @dev: device registering this clock

 * @name: name of this clock

 * @parent_name: name of clock's parent

 * @flags: framework-specific flags

 * @reg: register address to adjust divider

 * @shift: number of bits to shift the bitfield

 * @width: width of the bitfield

 * @clk_divider_flags: divider-specific flags for this clock

 * @lock: shared register lock for this clock

 */

struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,

		const char *parent_name, unsigned long flags,

		void __iomem *reg, u8 shift, u8 width,

		u8 clk_divider_flags, spinlock_t *lock)

{

	return _register_divider(dev, name, parent_name, flags, reg, shift,

			width, clk_divider_flags, NULL, lock);

}

EXPORT_SYMBOL_GPL(clk_hw_register_divider);



/**

 * clk_register_divider_table - register a table based divider clock with

 * the clock framework
@@ -517,11 +547,41 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name, 
		u8 clk_divider_flags, const struct clk_div_table *table,

		spinlock_t *lock)

{

	return _register_divider(dev, name, parent_name, flags, reg, shift,

	struct clk_hw *hw;



	hw =  _register_divider(dev, name, parent_name, flags, reg, shift,

			width, clk_divider_flags, table, lock);

	if (IS_ERR(hw))

		return ERR_CAST(hw);

	return hw->clk;

}

EXPORT_SYMBOL_GPL(clk_register_divider_table);



/**

 * clk_hw_register_divider_table - register a table based divider clock with

 * the clock framework

 * @dev: device registering this clock

 * @name: name of this clock

 * @parent_name: name of clock's parent

 * @flags: framework-specific flags

 * @reg: register address to adjust divider

 * @shift: number of bits to shift the bitfield

 * @width: width of the bitfield

 * @clk_divider_flags: divider-specific flags for this clock

 * @table: array of divider/value pairs ending with a div set to 0

 * @lock: shared register lock for this clock

 */

struct clk_hw *clk_hw_register_divider_table(struct device *dev,

		const char *name, const char *parent_name, unsigned long flags,

		void __iomem *reg, u8 shift, u8 width,

		u8 clk_divider_flags, const struct clk_div_table *table,

		spinlock_t *lock)

{

	return _register_divider(dev, name, parent_name, flags, reg, shift,

			width, clk_divider_flags, table, lock);

}

EXPORT_SYMBOL_GPL(clk_hw_register_divider_table);



void clk_unregister_divider(struct clk *clk)

{

	struct clk_divider *div;
@@ -537,3 +597,18 @@ void clk_unregister_divider(struct clk *clk) 
	kfree(div);

}

EXPORT_SYMBOL_GPL(clk_unregister_divider);



/**

 * clk_hw_unregister_divider - unregister a clk divider

 * @hw: hardware-specific clock data to unregister

 */

void clk_hw_unregister_divider(struct clk_hw *hw)

{

	struct clk_divider *div;



	div = to_clk_divider(hw);



	clk_hw_unregister(hw);

	kfree(div);

}

EXPORT_SYMBOL_GPL(clk_hw_unregister_divider);

drivers/clk/clk-fixed-factor.c

+35 −7
Original line number Diff line number Diff line
@@ -68,13 +68,14 @@ const struct clk_ops clk_fixed_factor_ops = { 
};

EXPORT_SYMBOL_GPL(clk_fixed_factor_ops);



struct clk *clk_register_fixed_factor(struct device *dev, const char *name,

		const char *parent_name, unsigned long flags,

struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,

		const char *name, const char *parent_name, unsigned long flags,

		unsigned int mult, unsigned int div)

{

	struct clk_fixed_factor *fix;

	struct clk_init_data init;

	struct clk *clk;

	struct clk_hw *hw;

	int ret;



	fix = kmalloc(sizeof(*fix), GFP_KERNEL);

	if (!fix)
@@ -91,12 +92,28 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name, 
	init.parent_names = &parent_name;

	init.num_parents = 1;



	clk = clk_register(dev, &fix->hw);



	if (IS_ERR(clk))

	hw = &fix->hw;

	ret = clk_hw_register(dev, hw);

	if (ret) {

		kfree(fix);

		hw = ERR_PTR(ret);

	}



	return clk;

	return hw;

}

EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor);



struct clk *clk_register_fixed_factor(struct device *dev, const char *name,

		const char *parent_name, unsigned long flags,

		unsigned int mult, unsigned int div)

{

	struct clk_hw *hw;



	hw = clk_hw_register_fixed_factor(dev, name, parent_name, flags, mult,

					  div);

	if (IS_ERR(hw))

		return ERR_CAST(hw);

	return hw->clk;

}

EXPORT_SYMBOL_GPL(clk_register_fixed_factor);
@@ -113,6 +130,17 @@ void clk_unregister_fixed_factor(struct clk *clk) 
}

EXPORT_SYMBOL_GPL(clk_unregister_fixed_factor);



void clk_hw_unregister_fixed_factor(struct clk_hw *hw)

{

	struct clk_fixed_factor *fix;



	fix = to_clk_fixed_factor(hw);



	clk_hw_unregister(hw);

	kfree(fix);

}

EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_factor);



#ifdef CONFIG_OF

/**

 * of_fixed_factor_clk_setup() - Setup function for simple fixed factor clock

drivers/clk/clk-fixed-rate.c

+36 −8
Original line number Diff line number Diff line
@@ -45,8 +45,8 @@ const struct clk_ops clk_fixed_rate_ops = { 
EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);



/**

 * clk_register_fixed_rate_with_accuracy - register fixed-rate clock with the

 *					   clock framework

 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with

 * the clock framework

 * @dev: device that is registering this clock

 * @name: name of this clock

 * @parent_name: name of clock's parent
@@ -54,13 +54,14 @@ EXPORT_SYMBOL_GPL(clk_fixed_rate_ops); 
 * @fixed_rate: non-adjustable clock rate

 * @fixed_accuracy: non-adjustable clock rate

 */

struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,

struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev,

		const char *name, const char *parent_name, unsigned long flags,

		unsigned long fixed_rate, unsigned long fixed_accuracy)

{

	struct clk_fixed_rate *fixed;

	struct clk *clk;

	struct clk_hw *hw;

	struct clk_init_data init;

	int ret;



	/* allocate fixed-rate clock */

	fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
@@ -79,22 +80,49 @@ struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, 
	fixed->hw.init = &init;



	/* register the clock */

	clk = clk_register(dev, &fixed->hw);

	if (IS_ERR(clk))

	hw = &fixed->hw;

	ret = clk_hw_register(dev, hw);

	if (ret) {

		kfree(fixed);

		hw = ERR_PTR(ret);

	}



	return hw;

}

EXPORT_SYMBOL_GPL(clk_hw_register_fixed_rate_with_accuracy);



struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,

		const char *name, const char *parent_name, unsigned long flags,

		unsigned long fixed_rate, unsigned long fixed_accuracy)

{

	struct clk_hw *hw;



	return clk;

	hw = clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name,

			flags, fixed_rate, fixed_accuracy);

	if (IS_ERR(hw))

		return ERR_CAST(hw);

	return hw->clk;

}

EXPORT_SYMBOL_GPL(clk_register_fixed_rate_with_accuracy);



/**

 * clk_register_fixed_rate - register fixed-rate clock with the clock framework

 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock

 * framework

 * @dev: device that is registering this clock

 * @name: name of this clock

 * @parent_name: name of clock's parent

 * @flags: framework-specific flags

 * @fixed_rate: non-adjustable clock rate

 */

struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name,

		const char *parent_name, unsigned long flags,

		unsigned long fixed_rate)

{

	return clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name,

						     flags, fixed_rate, 0);

}

EXPORT_SYMBOL_GPL(clk_hw_register_fixed_rate);



struct clk *clk_register_fixed_rate(struct device *dev, const char *name,

		const char *parent_name, unsigned long flags,

		unsigned long fixed_rate)

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