Commit 584fca11 authored by Lucas De Marchi's avatar Lucas De Marchi
Browse files

drm/i915/icl: use tc_port in MG_PLL macros 



Fix the TODO leftover in the code by changing the argument in MG_PLL
macros. The MG_PLL ids used to access the register values can be
converted from tc_port rather than port.

All these registers can use the TC port to calculate the right offsets
because they are only available for TC ports. The range (PORT_C onwards)
may not be stable and change from platform to platform. So by using the
TC id directly we avoid having to check for the platform in the "leaf
functions" and thus passing dev_priv around.

The helper functions were also renamed to use "tc" as prefix to make
them more generic.

v2: Improve commit message and fix checkpatch warning (from Paulo)

Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190125222444.19926-2-lucas.demarchi@intel.com
parent 789659f4

drivers/gpu/drm/i915/i915_reg.h

+26 −26
Original line number Diff line number Diff line
@@ -9554,7 +9554,7 @@ enum skl_power_gate { 
#define _MG_PLL3_ENABLE		0x46038

#define _MG_PLL4_ENABLE		0x4603C

/* Bits are the same as DPLL0_ENABLE */

#define MG_PLL_ENABLE(port)	_MMIO_PORT((port) - PORT_C, _MG_PLL1_ENABLE, \

#define MG_PLL_ENABLE(tc_port)	_MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \

					   _MG_PLL2_ENABLE)



#define _MG_REFCLKIN_CTL_PORT1				0x16892C
@@ -9563,7 +9563,7 @@ enum skl_power_gate { 
#define _MG_REFCLKIN_CTL_PORT4				0x16B92C

#define   MG_REFCLKIN_CTL_OD_2_MUX(x)			((x) << 8)

#define   MG_REFCLKIN_CTL_OD_2_MUX_MASK			(0x7 << 8)

#define MG_REFCLKIN_CTL(port) _MMIO_PORT((port) - PORT_C, \

#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \

					    _MG_REFCLKIN_CTL_PORT1, \

					    _MG_REFCLKIN_CTL_PORT2)
@@ -9575,7 +9575,7 @@ enum skl_power_gate { 
#define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK	(0xff << 16)

#define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x)		((x) << 8)

#define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK	(0xff << 8)

#define MG_CLKTOP2_CORECLKCTL1(port) _MMIO_PORT((port) - PORT_C, \

#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \

						   _MG_CLKTOP2_CORECLKCTL1_PORT1, \

						   _MG_CLKTOP2_CORECLKCTL1_PORT2)
@@ -9595,7 +9595,7 @@ enum skl_power_gate { 
#define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x)		((x) << 8)

#define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT		8

#define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK		(0xf << 8)

#define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \

#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \

						_MG_CLKTOP2_HSCLKCTL_PORT1, \

						_MG_CLKTOP2_HSCLKCTL_PORT2)
@@ -9609,7 +9609,7 @@ enum skl_power_gate { 
#define   MG_PLL_DIV0_FBDIV_FRAC(x)			((x) << 8)

#define   MG_PLL_DIV0_FBDIV_INT_MASK			(0xff << 0)

#define   MG_PLL_DIV0_FBDIV_INT(x)			((x) << 0)

#define MG_PLL_DIV0(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV0_PORT1, \

#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \

					_MG_PLL_DIV0_PORT2)



#define _MG_PLL_DIV1_PORT1				0x168A04
@@ -9624,7 +9624,7 @@ enum skl_power_gate { 
#define   MG_PLL_DIV1_NDIVRATIO(x)			((x) << 4)

#define   MG_PLL_DIV1_FBPREDIV_MASK			(0xf << 0)

#define   MG_PLL_DIV1_FBPREDIV(x)			((x) << 0)

#define MG_PLL_DIV1(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV1_PORT1, \

#define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \

					_MG_PLL_DIV1_PORT2)



#define _MG_PLL_LF_PORT1				0x168A08
@@ -9637,7 +9637,7 @@ enum skl_power_gate { 
#define   MG_PLL_LF_GAINCTRL(x)				((x) << 16)

#define   MG_PLL_LF_INT_COEFF(x)			((x) << 8)

#define   MG_PLL_LF_PROP_COEFF(x)			((x) << 0)

#define MG_PLL_LF(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_LF_PORT1, \

#define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \

				      _MG_PLL_LF_PORT2)



#define _MG_PLL_FRAC_LOCK_PORT1				0x168A0C
@@ -9650,7 +9650,7 @@ enum skl_power_gate { 
#define   MG_PLL_FRAC_LOCK_DCODITHEREN			(1 << 10)

#define   MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN		(1 << 8)

#define   MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x)		((x) << 0)

#define MG_PLL_FRAC_LOCK(port) _MMIO_PORT((port) - PORT_C, \

#define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \

					     _MG_PLL_FRAC_LOCK_PORT1, \

					     _MG_PLL_FRAC_LOCK_PORT2)
@@ -9664,7 +9664,7 @@ enum skl_power_gate { 
#define   MG_PLL_SSC_STEPNUM(x)				((x) << 10)

#define   MG_PLL_SSC_FLLEN				(1 << 9)

#define   MG_PLL_SSC_STEPSIZE(x)			((x) << 0)

#define MG_PLL_SSC(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_SSC_PORT1, \

#define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \

				       _MG_PLL_SSC_PORT2)



#define _MG_PLL_BIAS_PORT1				0x168A14
@@ -9684,7 +9684,7 @@ enum skl_power_gate { 
#define   MG_PLL_BIAS_VREF_RDAC_MASK			(0x7 << 5)

#define   MG_PLL_BIAS_IREFTRIM(x)			((x) << 0)

#define   MG_PLL_BIAS_IREFTRIM_MASK			(0x1f << 0)

#define MG_PLL_BIAS(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_BIAS_PORT1, \

#define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \

					_MG_PLL_BIAS_PORT2)



#define _MG_PLL_TDC_COLDST_BIAS_PORT1			0x168A18
@@ -9696,7 +9696,7 @@ enum skl_power_gate { 
#define   MG_PLL_TDC_COLDST_COLDSTART			(1 << 16)

#define   MG_PLL_TDC_TDCOVCCORR_EN			(1 << 2)

#define   MG_PLL_TDC_TDCSEL(x)				((x) << 0)

#define MG_PLL_TDC_COLDST_BIAS(port) _MMIO_PORT((port) - PORT_C, \

#define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \

						   _MG_PLL_TDC_COLDST_BIAS_PORT1, \

						   _MG_PLL_TDC_COLDST_BIAS_PORT2)

drivers/gpu/drm/i915/intel_ddi.c

+4 −3
Original line number Diff line number Diff line
@@ -1391,16 +1391,17 @@ static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 
static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,

				enum port port)

{

	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);

	u32 mg_pll_div0, mg_clktop_hsclkctl;

	u32 m1, m2_int, m2_frac, div1, div2, refclk;

	u64 tmp;



	refclk = dev_priv->cdclk.hw.ref;



	mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));

	mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(port));

	mg_pll_div0 = I915_READ(MG_PLL_DIV0(tc_port));

	mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port));



	m1 = I915_READ(MG_PLL_DIV1(port)) & MG_PLL_DIV1_FBPREDIV_MASK;

	m1 = I915_READ(MG_PLL_DIV1(tc_port)) & MG_PLL_DIV1_FBPREDIV_MASK;

	m2_int = mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;

	m2_frac = (mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?

		  (mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>

drivers/gpu/drm/i915/intel_display.c

+1 −1
Original line number Diff line number Diff line
@@ -9445,7 +9445,7 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv, 
		if (WARN_ON(!intel_dpll_is_combophy(id)))

			return;

	} else if (intel_port_is_tc(dev_priv, port)) {

		id = icl_port_to_mg_pll_id(port);

		id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, port));

	} else {

		WARN(1, "Invalid port %x\n", port);

		return;

drivers/gpu/drm/i915/intel_dpll_mgr.c

+39 −40
Original line number Diff line number Diff line
@@ -2639,14 +2639,14 @@ int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv, 
	return link_clock;

}



static enum port icl_mg_pll_id_to_port(enum intel_dpll_id id)

static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)

{

	return id - DPLL_ID_ICL_MGPLL1 + PORT_C;

	return id - DPLL_ID_ICL_MGPLL1;

}



enum intel_dpll_id icl_port_to_mg_pll_id(enum port port)

enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)

{

	return port - PORT_C + DPLL_ID_ICL_MGPLL1;

	return tc_port + DPLL_ID_ICL_MGPLL1;

}



bool intel_dpll_is_combophy(enum intel_dpll_id id)
@@ -2925,7 +2925,10 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, 
			ret = icl_calc_dpll_state(crtc_state, encoder, clock,

						  &pll_state);

		} else {

			min = icl_port_to_mg_pll_id(port);

			enum tc_port tc_port;



			tc_port = intel_port_to_tc(dev_priv, port);

			min = icl_tc_port_to_pll_id(tc_port);

			max = min;

			ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,

						    &pll_state);
@@ -2959,12 +2962,8 @@ static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id) 
		return CNL_DPLL_ENABLE(id);

	else if (id == DPLL_ID_ICL_TBTPLL)

		return TBT_PLL_ENABLE;

	else

		/*

		 * TODO: Make MG_PLL macros use

		 * tc port id instead of port id

		 */

		return MG_PLL_ENABLE(icl_mg_pll_id_to_port(id));



	return MG_PLL_ENABLE(icl_pll_id_to_tc_port(id));

}



static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
@@ -2974,7 +2973,6 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv, 
	const enum intel_dpll_id id = pll->info->id;

	intel_wakeref_t wakeref;

	bool ret = false;

	enum port port;

	u32 val;



	wakeref = intel_display_power_get_if_enabled(dev_priv,
@@ -2991,32 +2989,33 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv, 
		hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));

		hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));

	} else {

		port = icl_mg_pll_id_to_port(id);

		hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(port));

		enum tc_port tc_port = icl_pll_id_to_tc_port(id);



		hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(tc_port));

		hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;



		hw_state->mg_clktop2_coreclkctl1 =

			I915_READ(MG_CLKTOP2_CORECLKCTL1(port));

			I915_READ(MG_CLKTOP2_CORECLKCTL1(tc_port));

		hw_state->mg_clktop2_coreclkctl1 &=

			MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;



		hw_state->mg_clktop2_hsclkctl =

			I915_READ(MG_CLKTOP2_HSCLKCTL(port));

			I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port));

		hw_state->mg_clktop2_hsclkctl &=

			MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |

			MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |

			MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |

			MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;



		hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));

		hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(port));

		hw_state->mg_pll_lf = I915_READ(MG_PLL_LF(port));

		hw_state->mg_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(port));

		hw_state->mg_pll_ssc = I915_READ(MG_PLL_SSC(port));

		hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(tc_port));

		hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(tc_port));

		hw_state->mg_pll_lf = I915_READ(MG_PLL_LF(tc_port));

		hw_state->mg_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(tc_port));

		hw_state->mg_pll_ssc = I915_READ(MG_PLL_SSC(tc_port));



		hw_state->mg_pll_bias = I915_READ(MG_PLL_BIAS(port));

		hw_state->mg_pll_bias = I915_READ(MG_PLL_BIAS(tc_port));

		hw_state->mg_pll_tdc_coldst_bias =

			I915_READ(MG_PLL_TDC_COLDST_BIAS(port));

			I915_READ(MG_PLL_TDC_COLDST_BIAS(tc_port));



		if (dev_priv->cdclk.hw.ref == 38400) {

			hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
@@ -3051,7 +3050,7 @@ static void icl_mg_pll_write(struct drm_i915_private *dev_priv, 
			     struct intel_shared_dpll *pll)

{

	struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;

	enum port port = icl_mg_pll_id_to_port(pll->info->id);

	enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);

	u32 val;



	/*
@@ -3060,41 +3059,41 @@ static void icl_mg_pll_write(struct drm_i915_private *dev_priv, 
	 * during the calc/readout phase if the mask depends on some other HW

	 * state like refclk, see icl_calc_mg_pll_state().

	 */

	val = I915_READ(MG_REFCLKIN_CTL(port));

	val = I915_READ(MG_REFCLKIN_CTL(tc_port));

	val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;

	val |= hw_state->mg_refclkin_ctl;

	I915_WRITE(MG_REFCLKIN_CTL(port), val);

	I915_WRITE(MG_REFCLKIN_CTL(tc_port), val);



	val = I915_READ(MG_CLKTOP2_CORECLKCTL1(port));

	val = I915_READ(MG_CLKTOP2_CORECLKCTL1(tc_port));

	val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;

	val |= hw_state->mg_clktop2_coreclkctl1;

	I915_WRITE(MG_CLKTOP2_CORECLKCTL1(port), val);

	I915_WRITE(MG_CLKTOP2_CORECLKCTL1(tc_port), val);



	val = I915_READ(MG_CLKTOP2_HSCLKCTL(port));

	val = I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port));

	val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |

		 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |

		 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |

		 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);

	val |= hw_state->mg_clktop2_hsclkctl;

	I915_WRITE(MG_CLKTOP2_HSCLKCTL(port), val);

	I915_WRITE(MG_CLKTOP2_HSCLKCTL(tc_port), val);



	I915_WRITE(MG_PLL_DIV0(port), hw_state->mg_pll_div0);

	I915_WRITE(MG_PLL_DIV1(port), hw_state->mg_pll_div1);

	I915_WRITE(MG_PLL_LF(port), hw_state->mg_pll_lf);

	I915_WRITE(MG_PLL_FRAC_LOCK(port), hw_state->mg_pll_frac_lock);

	I915_WRITE(MG_PLL_SSC(port), hw_state->mg_pll_ssc);

	I915_WRITE(MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);

	I915_WRITE(MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);

	I915_WRITE(MG_PLL_LF(tc_port), hw_state->mg_pll_lf);

	I915_WRITE(MG_PLL_FRAC_LOCK(tc_port), hw_state->mg_pll_frac_lock);

	I915_WRITE(MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);



	val = I915_READ(MG_PLL_BIAS(port));

	val = I915_READ(MG_PLL_BIAS(tc_port));

	val &= ~hw_state->mg_pll_bias_mask;

	val |= hw_state->mg_pll_bias;

	I915_WRITE(MG_PLL_BIAS(port), val);

	I915_WRITE(MG_PLL_BIAS(tc_port), val);



	val = I915_READ(MG_PLL_TDC_COLDST_BIAS(port));

	val = I915_READ(MG_PLL_TDC_COLDST_BIAS(tc_port));

	val &= ~hw_state->mg_pll_tdc_coldst_bias_mask;

	val |= hw_state->mg_pll_tdc_coldst_bias;

	I915_WRITE(MG_PLL_TDC_COLDST_BIAS(port), val);

	I915_WRITE(MG_PLL_TDC_COLDST_BIAS(tc_port), val);



	POSTING_READ(MG_PLL_TDC_COLDST_BIAS(port));

	POSTING_READ(MG_PLL_TDC_COLDST_BIAS(tc_port));

}



static void icl_pll_enable(struct drm_i915_private *dev_priv,

drivers/gpu/drm/i915/intel_dpll_mgr.h

+1 −1
Original line number Diff line number Diff line
@@ -344,7 +344,7 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, 
int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,

			       u32 pll_id);

int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);

enum intel_dpll_id icl_port_to_mg_pll_id(enum port port);

enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);

bool intel_dpll_is_combophy(enum intel_dpll_id id);



#endif /* _INTEL_DPLL_MGR_H_ */

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