Commit 584f800c authored by Nagarjuna Kristam's avatar Nagarjuna Kristam Committed by Thierry Reding
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arm64: tegra: Add XUDC node for Tegra186



Tegra186 has one XUSB device mode controller, which can be operated in
HS and SS modes. Add DT entry for XUSB device mode controller.

Signed-off-by: default avatarNagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 6b3d8593
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+19 −0
Original line number Diff line number Diff line
@@ -572,6 +572,25 @@
		nvidia,xusb-padctl = <&padctl>;
	};

	usb@3550000 {
		compatible = "nvidia,tegra186-xudc";
		reg = <0x0 0x03550000 0x0 0x8000>,
		      <0x0 0x03558000 0x0 0x1000>;
		reg-names = "base", "fpci";
		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>,
			 <&bpmp TEGRA186_CLK_XUSB_SS>,
			 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
			 <&bpmp TEGRA186_CLK_XUSB_FS>;
		clock-names = "dev", "ss", "ss_src", "fs_src";
		iommus = <&smmu TEGRA186_SID_XUSB_DEV>;
		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
				<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
		power-domain-names = "dev", "ss";
		nvidia,xusb-padctl = <&padctl>;
		status = "disabled";
	};

	fuse@3820000 {
		compatible = "nvidia,tegra186-efuse";
		reg = <0x0 0x03820000 0x0 0x10000>;