Commit 57fe8fd2 authored by Igor Russkikh's avatar Igor Russkikh Committed by David S. Miller
Browse files

net: atlantic: HW bindings for A2 RFP 



RPF is one of the modules which has been significantly
changed/extended on A2.

This patch adds the necessary A2 register definitions
for RPF, which are used in follow-up patches.

Signed-off-by: default avatarIgor Russkikh <irusskikh@marvell.com>
Co-developed-by: default avatarDmitry Bogdanov <dbogdanov@marvell.com>
Signed-off-by: default avatarDmitry Bogdanov <dbogdanov@marvell.com>
Signed-off-by: default avatarMark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent b3f0c79c

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c

+14 −0
Original line number Diff line number Diff line
@@ -693,6 +693,13 @@ void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw, 
			    HW_ATL_RPFL2MC_ENF_SHIFT, l2multicast_flr_en);

}



u32 hw_atl_rpfl2promiscuous_mode_en_get(struct aq_hw_s *aq_hw)

{

	return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPFL2PROMIS_MODE_ADR,

				  HW_ATL_RPFL2PROMIS_MODE_MSK,

				  HW_ATL_RPFL2PROMIS_MODE_SHIFT);

}



void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,

					 u32 l2promiscuous_mode_en)

{
@@ -867,6 +874,13 @@ void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw, 
			    vlan_prom_mode_en);

}



u32 hw_atl_rpf_vlan_prom_mode_en_get(struct aq_hw_s *aq_hw)

{

	return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR,

				  HW_ATL_RPF_VL_PROMIS_MODE_MSK,

				  HW_ATL_RPF_VL_PROMIS_MODE_SHIFT);

}



void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,

						 u32 vlan_acc_untagged_packets)

{

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h

+6 −0
Original line number Diff line number Diff line
@@ -349,6 +349,9 @@ void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw, 
				      u32 l2multicast_flr_en,

				      u32 filter);



/* get l2 promiscuous mode enable */

u32 hw_atl_rpfl2promiscuous_mode_en_get(struct aq_hw_s *aq_hw);



/* set l2 promiscuous mode enable */

void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,

					 u32 l2promiscuous_mode_en);
@@ -420,6 +423,9 @@ void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht); 
void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw,

				      u32 vlan_prom_mode_en);



/* Get VLAN promiscuous mode enable */

u32 hw_atl_rpf_vlan_prom_mode_en_get(struct aq_hw_s *aq_hw);



/* Set VLAN untagged action */

void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw,

				      u32 vlan_untagged_act);

drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.c

+74 −0
Original line number Diff line number Diff line
@@ -7,6 +7,80 @@ 
#include "hw_atl2_llh_internal.h"

#include "aq_hw_utils.h"



void hw_atl2_rpf_rss_hash_type_set(struct aq_hw_s *aq_hw, u32 rss_hash_type)

{

	aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_ADR,

			    HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_MSK,

			    HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_SHIFT,

			    rss_hash_type);

}



/* rpf */



void hw_atl2_rpf_new_enable_set(struct aq_hw_s *aq_hw, u32 enable)

{

	aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_NEW_EN_ADR,

			    HW_ATL2_RPF_NEW_EN_MSK,

			    HW_ATL2_RPF_NEW_EN_SHIFT,

			    enable);

}



void hw_atl2_rpfl2_uc_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filter)

{

	aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPFL2UC_TAG_ADR(filter),

			    HW_ATL2_RPFL2UC_TAG_MSK,

			    HW_ATL2_RPFL2UC_TAG_SHIFT,

			    tag);

}



void hw_atl2_rpfl2_bc_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag)

{

	aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_L2_BC_TAG_ADR,

			    HW_ATL2_RPF_L2_BC_TAG_MSK,

			    HW_ATL2_RPF_L2_BC_TAG_SHIFT,

			    tag);

}



void hw_atl2_new_rpf_rss_redir_set(struct aq_hw_s *aq_hw, u32 tc, u32 index,

				   u32 queue)

{

	aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_RSS_REDIR_ADR(tc, index),

			    HW_ATL2_RPF_RSS_REDIR_MSK(tc),

			    HW_ATL2_RPF_RSS_REDIR_SHIFT(tc),

			    queue);

}



void hw_atl2_rpf_vlan_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filter)

{

	aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_VL_TAG_ADR(filter),

			    HW_ATL2_RPF_VL_TAG_MSK,

			    HW_ATL2_RPF_VL_TAG_SHIFT,

			    tag);

}



/* set action resolver record */

void hw_atl2_rpf_act_rslvr_record_set(struct aq_hw_s *aq_hw, u8 location,

				      u32 tag, u32 mask, u32 action)

{

	aq_hw_write_reg(aq_hw,

			HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_ADR(location),

			tag);

	aq_hw_write_reg(aq_hw,

			HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_ADR(location),

			mask);

	aq_hw_write_reg(aq_hw,

			HW_ATL2_RPF_ACT_RSLVR_ACTN_ADR(location),

			action);

}



void hw_atl2_rpf_act_rslvr_section_en_set(struct aq_hw_s *aq_hw, u32 sections)

{

	aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_REC_TAB_EN_ADR,

			    HW_ATL2_RPF_REC_TAB_EN_MSK,

			    HW_ATL2_RPF_REC_TAB_EN_SHIFT,

			    sections);

}



void hw_atl2_mif_shared_buf_get(struct aq_hw_s *aq_hw, int offset, u32 *data,

				int len)

{

drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.h

+26 −0
Original line number Diff line number Diff line
@@ -10,6 +10,32 @@ 


struct aq_hw_s;



/** Set RSS HASH type */

void hw_atl2_rpf_rss_hash_type_set(struct aq_hw_s *aq_hw, u32 rss_hash_type);



/* set new RPF enable */

void hw_atl2_rpf_new_enable_set(struct aq_hw_s *aq_hw, u32 enable);



/* set l2 unicast filter tag */

void hw_atl2_rpfl2_uc_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filter);



/* set l2 broadcast filter tag */

void hw_atl2_rpfl2_bc_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag);



/* set new rss redirection table */

void hw_atl2_new_rpf_rss_redir_set(struct aq_hw_s *aq_hw, u32 tc, u32 index,

				   u32 queue);



/* Set VLAN filter tag */

void hw_atl2_rpf_vlan_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filter);



/* set action resolver record */

void hw_atl2_rpf_act_rslvr_record_set(struct aq_hw_s *aq_hw, u8 location,

				      u32 tag, u32 mask, u32 action);



/* set enable action resolver section */

void hw_atl2_rpf_act_rslvr_section_en_set(struct aq_hw_s *aq_hw, u32 sections);



/* get data from firmware shared input buffer */

void hw_atl2_mif_shared_buf_get(struct aq_hw_s *aq_hw, int offset, u32 *data,

				int len);

drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh_internal.h

+164 −0
Original line number Diff line number Diff line
@@ -6,6 +6,170 @@ 
#ifndef HW_ATL2_LLH_INTERNAL_H

#define HW_ATL2_LLH_INTERNAL_H



/* RX pif_rpf_rss_hash_type_i Bitfield Definitions

 */

#define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_ADR 0x000054C8

#define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_MSK 0x000001FF

#define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_MSKN 0xFFFFFE00

#define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_SHIFT 0

#define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_WIDTH 9



/* rx rpf_new_rpf_en bitfield definitions

 * preprocessor definitions for the bitfield "rpf_new_rpf_en_i".

 * port="pif_rpf_new_rpf_en_i

 */



/* register address for bitfield rpf_new_rpf_en */

#define HW_ATL2_RPF_NEW_EN_ADR 0x00005104

/* bitmask for bitfield rpf_new_rpf_en */

#define HW_ATL2_RPF_NEW_EN_MSK 0x00000800

/* inverted bitmask for bitfield rpf_new_rpf_en */

#define HW_ATL2_RPF_NEW_EN_MSKN 0xfffff7ff

/* lower bit position of bitfield rpf_new_rpf_en */

#define HW_ATL2_RPF_NEW_EN_SHIFT 11

/* width of bitfield rpf_new_rpf_en */

#define HW_ATL2_RPF_NEW_EN_WIDTH 1

/* default value of bitfield rpf_new_rpf_en */

#define HW_ATL2_RPF_NEW_EN_DEFAULT 0x0



/* rx l2_uc_req_tag0{f}[5:0] bitfield definitions

 * preprocessor definitions for the bitfield "l2_uc_req_tag0{f}[7:0]".

 * parameter: filter {f} | stride size 0x8 | range [0, 37]

 * port="pif_rpf_l2_uc_req_tag0[5:0]"

 */



/* register address for bitfield l2_uc_req_tag0{f}[2:0] */

#define HW_ATL2_RPFL2UC_TAG_ADR(filter) (0x00005114 + (filter) * 0x8)

/* bitmask for bitfield l2_uc_req_tag0{f}[2:0] */

#define HW_ATL2_RPFL2UC_TAG_MSK 0x0FC00000

/* inverted bitmask for bitfield l2_uc_req_tag0{f}[2:0] */

#define HW_ATL2_RPFL2UC_TAG_MSKN 0xF03FFFFF

/* lower bit position of bitfield l2_uc_req_tag0{f}[2:0] */

#define HW_ATL2_RPFL2UC_TAG_SHIFT 22

/* width of bitfield l2_uc_req_tag0{f}[2:0] */

#define HW_ATL2_RPFL2UC_TAG_WIDTH 6

/* default value of bitfield l2_uc_req_tag0{f}[2:0] */

#define HW_ATL2_RPFL2UC_TAG_DEFAULT 0x0



/* rpf_l2_bc_req_tag[5:0] bitfield definitions

 * preprocessor definitions for the bitfield "rpf_l2_bc_req_tag[5:0]".

 * port="pifrpf_l2_bc_req_tag_i[5:0]"

 */



/* register address for bitfield rpf_l2_bc_req_tag */

#define HW_ATL2_RPF_L2_BC_TAG_ADR 0x000050F0

/* bitmask for bitfield rpf_l2_bc_req_tag */

#define HW_ATL2_RPF_L2_BC_TAG_MSK 0x0000003F

/* inverted bitmask for bitfield rpf_l2_bc_req_tag */

#define HW_ATL2_RPF_L2_BC_TAG_MSKN 0xffffffc0

/* lower bit position of bitfield rpf_l2_bc_req_tag */

#define HW_ATL2_RPF_L2_BC_TAG_SHIFT 0

/* width of bitfield rpf_l2_bc_req_tag */

#define HW_ATL2_RPF_L2_BC_TAG_WIDTH 6

/* default value of bitfield rpf_l2_bc_req_tag */

#define HW_ATL2_RPF_L2_BC_TAG_DEFAULT 0x0



/* rx rpf_rss_red1_data_[4:0] bitfield definitions

 * preprocessor definitions for the bitfield "rpf_rss_red1_data[4:0]".

 * port="pif_rpf_rss_red1_data_i[4:0]"

 */



/* register address for bitfield rpf_rss_red1_data[4:0] */

#define HW_ATL2_RPF_RSS_REDIR_ADR(TC, INDEX) (0x00006200 + \

					(0x100 * !!((TC) > 3)) + (INDEX) * 4)

/* bitmask for bitfield rpf_rss_red1_data[4:0] */

#define HW_ATL2_RPF_RSS_REDIR_MSK(TC)  (0x00000001F << (5 * ((TC) % 4)))

/* lower bit position of bitfield rpf_rss_red1_data[4:0] */

#define HW_ATL2_RPF_RSS_REDIR_SHIFT(TC) (5 * ((TC) % 4))

/* width of bitfield rpf_rss_red1_data[4:0] */

#define HW_ATL2_RPF_RSS_REDIR_WIDTH 5

/* default value of bitfield rpf_rss_red1_data[4:0] */

#define HW_ATL2_RPF_RSS_REDIR_DEFAULT 0x0



/* rx vlan_req_tag0{f}[3:0] bitfield definitions

 * preprocessor definitions for the bitfield "vlan_req_tag0{f}[3:0]".

 * parameter: filter {f} | stride size 0x4 | range [0, 15]

 * port="pif_rpf_vlan_req_tag0[3:0]"

 */



/* register address for bitfield vlan_req_tag0{f}[3:0] */

#define HW_ATL2_RPF_VL_TAG_ADR(filter) (0x00005290 + (filter) * 0x4)

/* bitmask for bitfield vlan_req_tag0{f}[3:0] */

#define HW_ATL2_RPF_VL_TAG_MSK 0x0000F000

/* inverted bitmask for bitfield vlan_req_tag0{f}[3:0] */

#define HW_ATL2_RPF_VL_TAG_MSKN 0xFFFF0FFF

/* lower bit position of bitfield vlan_req_tag0{f}[3:0] */

#define HW_ATL2_RPF_VL_TAG_SHIFT 12

/* width of bitfield vlan_req_tag0{f}[3:0] */

#define HW_ATL2_RPF_VL_TAG_WIDTH 4

/* default value of bitfield vlan_req_tag0{f}[3:0] */

#define HW_ATL2_RPF_VL_TAG_DEFAULT 0x0



/* ahb_mem_addr{f}[31:0] Bitfield Definitions

 * Preprocessor definitions for the bitfield "ahb_mem_addr{f}[31:0]".

 * Parameter: filter {f} | stride size 0x10 | range [0, 127]

 * PORT="ahb_mem_addr{f}[31:0]"

 */



/* Register address for bitfield ahb_mem_addr{f}[31:0] */

#define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_ADR(filter) \

	(0x00014000u + (filter) * 0x10)

/* Bitmask for bitfield ahb_mem_addr{f}[31:0] */

#define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_MSK 0xFFFFFFFFu

/* Inverted bitmask for bitfield ahb_mem_addr{f}[31:0] */

#define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_MSKN 0x00000000u

/* Lower bit position of bitfield ahb_mem_addr{f}[31:0] */

#define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_SHIFT 0

/* Width of bitfield ahb_mem_addr{f}[31:0] */

#define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_WIDTH 31

/* Default value of bitfield ahb_mem_addr{f}[31:0] */

#define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_DEFAULT 0x0



/* Register address for bitfield ahb_mem_addr{f}[31:0] */

#define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_ADR(filter) \

	(0x00014004u + (filter) * 0x10)

/* Bitmask for bitfield ahb_mem_addr{f}[31:0] */

#define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_MSK 0xFFFFFFFFu

/* Inverted bitmask for bitfield ahb_mem_addr{f}[31:0] */

#define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_MSKN 0x00000000u

/* Lower bit position of bitfield ahb_mem_addr{f}[31:0] */

#define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_SHIFT 0

/* Width of bitfield ahb_mem_addr{f}[31:0] */

#define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_WIDTH 31

/* Default value of bitfield ahb_mem_addr{f}[31:0] */

#define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_DEFAULT 0x0



/* Register address for bitfield ahb_mem_addr{f}[31:0] */

#define HW_ATL2_RPF_ACT_RSLVR_ACTN_ADR(filter) \

	(0x00014008u + (filter) * 0x10)

/* Bitmask for bitfield ahb_mem_addr{f}[31:0] */

#define HW_ATL2_RPF_ACT_RSLVR_ACTN_MSK 0x000007FFu

/* Inverted bitmask for bitfield ahb_mem_addr{f}[31:0] */

#define HW_ATL2_RPF_ACT_RSLVR_ACTN_MSKN 0xFFFFF800u

/* Lower bit position of bitfield ahb_mem_addr{f}[31:0] */

#define HW_ATL2_RPF_ACT_RSLVR_ACTN_SHIFT 0

/* Width of bitfield ahb_mem_addr{f}[31:0] */

#define HW_ATL2_RPF_ACT_RSLVR_ACTN_WIDTH 10

/* Default value of bitfield ahb_mem_addr{f}[31:0] */

#define HW_ATL2_RPF_ACT_RSLVR_ACTN_DEFAULT 0x0



/* rpf_rec_tab_en[15:0] Bitfield Definitions

 * Preprocessor definitions for the bitfield "rpf_rec_tab_en[15:0]".

 * PORT="pif_rpf_rec_tab_en[15:0]"

 */

/* Register address for bitfield rpf_rec_tab_en[15:0] */

#define HW_ATL2_RPF_REC_TAB_EN_ADR 0x00006ff0u

/* Bitmask for bitfield rpf_rec_tab_en[15:0] */

#define HW_ATL2_RPF_REC_TAB_EN_MSK 0x0000FFFFu

/* Inverted bitmask for bitfield rpf_rec_tab_en[15:0] */

#define HW_ATL2_RPF_REC_TAB_EN_MSKN 0xFFFF0000u

/* Lower bit position of bitfield rpf_rec_tab_en[15:0] */

#define HW_ATL2_RPF_REC_TAB_EN_SHIFT 0

/* Width of bitfield rpf_rec_tab_en[15:0] */

#define HW_ATL2_RPF_REC_TAB_EN_WIDTH 16

/* Default value of bitfield rpf_rec_tab_en[15:0] */

#define HW_ATL2_RPF_REC_TAB_EN_DEFAULT 0x0



/* Register address for firmware shared input buffer */

#define HW_ATL2_MIF_SHARED_BUFFER_IN_ADR(dword) (0x00012000U + (dword) * 0x4U)

/* Register address for firmware shared output buffer */

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