Commit 57e2a99f authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt
Browse files

powerpc: Add memory management headers for new 64-bit BookE 



This adds the PTE and pgtable format definitions, along with changes
to the kernel memory map and other definitions related to implementing
support for 64-bit Book3E. This also shields some asm-offset bits that
are currently only relevant on 32-bit

We also move the definition of the "linux" page size constants to
the common mmu.h file and add a few sizes that are relevant to
embedded processors.

Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent 0257c99c

arch/powerpc/include/asm/mmu-book3e.h

+27 −0
Original line number Diff line number Diff line
@@ -170,6 +170,33 @@ typedef struct { 
	unsigned int	active;

	unsigned long	vdso_base;

} mm_context_t;



/* Page size definitions, common between 32 and 64-bit

 *

 *    shift : is the "PAGE_SHIFT" value for that page size

 *    penc  : is the pte encoding mask

 *

 */

struct mmu_psize_def

{

	unsigned int	shift;	/* number of bits */

	unsigned int	enc;	/* PTE encoding */

};

extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];



/* The page sizes use the same names as 64-bit hash but are

 * constants

 */

#if defined(CONFIG_PPC_4K_PAGES)

#define mmu_virtual_psize	MMU_PAGE_4K

#elif defined(CONFIG_PPC_64K_PAGES)

#define mmu_virtual_psize	MMU_PAGE_64K

#else

#error Unsupported page size

#endif



extern int mmu_linear_psize;



#endif /* !__ASSEMBLY__ */



#endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */

arch/powerpc/include/asm/mmu-hash64.h

+0 −20
Original line number Diff line number Diff line
@@ -138,26 +138,6 @@ struct mmu_psize_def 


#endif /* __ASSEMBLY__ */



/*

 * The kernel use the constants below to index in the page sizes array.

 * The use of fixed constants for this purpose is better for performances

 * of the low level hash refill handlers.

 *

 * A non supported page size has a "shift" field set to 0

 *

 * Any new page size being implemented can get a new entry in here. Whether

 * the kernel will use it or not is a different matter though. The actual page

 * size used by hugetlbfs is not defined here and may be made variable

 */



#define MMU_PAGE_4K		0	/* 4K */

#define MMU_PAGE_64K		1	/* 64K */

#define MMU_PAGE_64K_AP		2	/* 64K Admixed (in a 4K segment) */

#define MMU_PAGE_1M		3	/* 1M */

#define MMU_PAGE_16M		4	/* 16M */

#define MMU_PAGE_16G		5	/* 16G */

#define MMU_PAGE_COUNT		6



/*

 * Segment sizes.

 * These are the values used by hardware in the B field of

arch/powerpc/include/asm/mmu.h

+37 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#define MMU_FTR_TYPE_40x		ASM_CONST(0x00000004)

#define MMU_FTR_TYPE_44x		ASM_CONST(0x00000008)

#define MMU_FTR_TYPE_FSL_E		ASM_CONST(0x00000010)

#define MMU_FTR_TYPE_3E			ASM_CONST(0x00000020)



/*

 * This is individual features
@@ -73,6 +74,41 @@ extern void early_init_mmu_secondary(void); 


#endif /* !__ASSEMBLY__ */



/* The kernel use the constants below to index in the page sizes array.

 * The use of fixed constants for this purpose is better for performances

 * of the low level hash refill handlers.

 *

 * A non supported page size has a "shift" field set to 0

 *

 * Any new page size being implemented can get a new entry in here. Whether

 * the kernel will use it or not is a different matter though. The actual page

 * size used by hugetlbfs is not defined here and may be made variable

 *

 * Note: This array ended up being a false good idea as it's growing to the

 * point where I wonder if we should replace it with something different,

 * to think about, feedback welcome. --BenH.

 */



/* There are #define as they have to be used in assembly

 *

 * WARNING: If you change this list, make sure to update the array of

 * names currently in arch/powerpc/mm/hugetlbpage.c or bad things will

 * happen

 */

#define MMU_PAGE_4K	0

#define MMU_PAGE_16K	1

#define MMU_PAGE_64K	2

#define MMU_PAGE_64K_AP	3	/* "Admixed pages" (hash64 only) */

#define MMU_PAGE_256K	4

#define MMU_PAGE_1M	5

#define MMU_PAGE_8M	6

#define MMU_PAGE_16M	7

#define MMU_PAGE_256M	8

#define MMU_PAGE_1G	9

#define MMU_PAGE_16G	10

#define MMU_PAGE_64G	11

#define MMU_PAGE_COUNT	12





#if defined(CONFIG_PPC_STD_MMU_64)

/* 64-bit classic hash table MMU */
@@ -94,5 +130,6 @@ extern void early_init_mmu_secondary(void); 
#  include <asm/mmu-8xx.h>

#endif





#endif /* __KERNEL__ */

#endif /* _ASM_POWERPC_MMU_H_ */

arch/powerpc/include/asm/page.h

+4 −0
Original line number Diff line number Diff line
@@ -139,7 +139,11 @@ extern phys_addr_t kernstart_addr; 
 * Don't compare things with KERNELBASE or PAGE_OFFSET to test for

 * "kernelness", use is_kernel_addr() - it should do what you want.

 */

#ifdef CONFIG_PPC_BOOK3E_64

#define is_kernel_addr(x)	((x) >= 0x8000000000000000ul)

#else

#define is_kernel_addr(x)	((x) >= PAGE_OFFSET)

#endif



#ifndef __ASSEMBLY__

arch/powerpc/include/asm/page_64.h

+10 −0
Original line number Diff line number Diff line
@@ -135,12 +135,22 @@ extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start, 
#endif /* __ASSEMBLY__ */

#else

#define slice_init()

#ifdef CONFIG_PPC_STD_MMU_64

#define get_slice_psize(mm, addr)	((mm)->context.user_psize)

#define slice_set_user_psize(mm, psize)		\

do {						\

	(mm)->context.user_psize = (psize);	\

	(mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \

} while (0)

#else /* CONFIG_PPC_STD_MMU_64 */

#ifdef CONFIG_PPC_64K_PAGES

#define get_slice_psize(mm, addr)	MMU_PAGE_64K

#else /* CONFIG_PPC_64K_PAGES */

#define get_slice_psize(mm, addr)	MMU_PAGE_4K

#endif /* !CONFIG_PPC_64K_PAGES */

#define slice_set_user_psize(mm, psize)	do { BUG(); } while(0)

#endif /* !CONFIG_PPC_STD_MMU_64 */



#define slice_set_range_psize(mm, start, len, psize)	\

	slice_set_user_psize((mm), (psize))

#define slice_mm_new_context(mm)	1

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