Commit 57d3b816 authored by Elliot Berman's avatar Elliot Berman Committed by Bjorn Andersson
Browse files

firmware: qcom_scm: Remove thin wrappers 



qcom_scm-32 and qcom_scm-64 implementations are nearly identical, so
make qcom_scm_call and qcom_scm_call_atomic unique to each and the SCM
descriptor creation common to each. There are the following catches:
- __qcom_scm_is_call_available is still in each -32,-64 implementation
  as the argument is unique to each convention
- For some functions, only one implementation was provided in -32 or
  -64. The actual implementation was moved into qcom_scm.c
- io_writel and io_readl in -64 were non-atomic calls and in -32 they
  were. Atomic is the better option, so use it.

Tested-by: Brian Masney <masneyb@onstation.org> # arm32
Tested-by: default avatarStephan Gerhold <stephan@gerhold.net>
Signed-off-by: default avatarElliot Berman <eberman@codeaurora.org>
Link: https://lore.kernel.org/r/1578431066-19600-17-git-send-email-eberman@codeaurora.org


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 65f0c90b

drivers/firmware/qcom_scm-32.c

+4 −457
Original line number Diff line number Diff line
@@ -15,75 +15,8 @@ 


#include "qcom_scm.h"



#define QCOM_SCM_FLAG_COLDBOOT_CPU0	0x00

#define QCOM_SCM_FLAG_COLDBOOT_CPU1	0x01

#define QCOM_SCM_FLAG_COLDBOOT_CPU2	0x08

#define QCOM_SCM_FLAG_COLDBOOT_CPU3	0x20



#define QCOM_SCM_FLAG_WARMBOOT_CPU0	0x04

#define QCOM_SCM_FLAG_WARMBOOT_CPU1	0x02

#define QCOM_SCM_FLAG_WARMBOOT_CPU2	0x10

#define QCOM_SCM_FLAG_WARMBOOT_CPU3	0x40



struct qcom_scm_entry {

	int flag;

	void *entry;

};



static struct qcom_scm_entry qcom_scm_wb[] = {

	{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },

	{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 },

	{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 },

	{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },

};



static DEFINE_MUTEX(qcom_scm_lock);



#define MAX_QCOM_SCM_ARGS 10

#define MAX_QCOM_SCM_RETS 3



enum qcom_scm_arg_types {

	QCOM_SCM_VAL,

	QCOM_SCM_RO,

	QCOM_SCM_RW,

	QCOM_SCM_BUFVAL,

};



#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\

			   (((a) & 0x3) << 4) | \

			   (((b) & 0x3) << 6) | \

			   (((c) & 0x3) << 8) | \

			   (((d) & 0x3) << 10) | \

			   (((e) & 0x3) << 12) | \

			   (((f) & 0x3) << 14) | \

			   (((g) & 0x3) << 16) | \

			   (((h) & 0x3) << 18) | \

			   (((i) & 0x3) << 20) | \

			   (((j) & 0x3) << 22) | \

			   ((num) & 0xf))



#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)



/**

 * struct qcom_scm_desc

 * @arginfo:	Metadata describing the arguments in args[]

 * @args:	The array of arguments for the secure syscall

 */

struct qcom_scm_desc {

	u32 svc;

	u32 cmd;

	u32 arginfo;

	u64 args[MAX_QCOM_SCM_ARGS];

	u32 owner;

};



/**

 * struct qcom_scm_res

 * @result:	The values returned by the secure syscall

 */

struct qcom_scm_res {

	u64 result[MAX_QCOM_SCM_RETS];

};



/**

 * struct arm_smccc_args
@@ -196,7 +129,7 @@ static void __scm_legacy_do(const struct arm_smccc_args *smc, 
 * and response buffers is taken care of by qcom_scm_call; however, callers are

 * responsible for any other cached buffers passed over to the secure world.

 */

static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,

int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,

			 struct qcom_scm_res *res)

{

	u8 arglen = desc->arginfo & 0xf;
@@ -285,7 +218,7 @@ out: 
 * This shall only be used with commands that are guaranteed to be

 * uninterruptable, atomic and SMP safe.

 */

static int qcom_scm_call_atomic(struct device *unused,

int qcom_scm_call_atomic(struct device *unused,

			 const struct qcom_scm_desc *desc,

			 struct qcom_scm_res *res)

{
@@ -309,113 +242,6 @@ static int qcom_scm_call_atomic(struct device *unused, 
	return smc_res.a0;

}



/**

 * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus

 * @entry: Entry point function for the cpus

 * @cpus: The cpumask of cpus that will use the entry point

 *

 * Set the cold boot address of the cpus. Any cpu outside the supported

 * range would be removed from the cpu present mask.

 */

int __qcom_scm_set_cold_boot_addr(struct device *dev, void *entry,

				  const cpumask_t *cpus)

{

	int flags = 0;

	int cpu;

	int scm_cb_flags[] = {

		QCOM_SCM_FLAG_COLDBOOT_CPU0,

		QCOM_SCM_FLAG_COLDBOOT_CPU1,

		QCOM_SCM_FLAG_COLDBOOT_CPU2,

		QCOM_SCM_FLAG_COLDBOOT_CPU3,

	};

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_BOOT,

		.cmd = QCOM_SCM_BOOT_SET_ADDR,

	};



	if (!cpus || (cpus && cpumask_empty(cpus)))

		return -EINVAL;



	for_each_cpu(cpu, cpus) {

		if (cpu < ARRAY_SIZE(scm_cb_flags))

			flags |= scm_cb_flags[cpu];

		else

			set_cpu_present(cpu, false);

	}



	desc.args[0] = flags;

	desc.args[1] = virt_to_phys(entry);

	desc.arginfo = QCOM_SCM_ARGS(2);



	return qcom_scm_call_atomic(dev, &desc, NULL);

}



/**

 * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus

 * @entry: Entry point function for the cpus

 * @cpus: The cpumask of cpus that will use the entry point

 *

 * Set the Linux entry point for the SCM to transfer control to when coming

 * out of a power down. CPU power down may be executed on cpuidle or hotplug.

 */

int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,

				  const cpumask_t *cpus)

{

	int ret;

	int flags = 0;

	int cpu;

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_BOOT,

		.cmd = QCOM_SCM_BOOT_SET_ADDR,

	};



	/*

	 * Reassign only if we are switching from hotplug entry point

	 * to cpuidle entry point or vice versa.

	 */

	for_each_cpu(cpu, cpus) {

		if (entry == qcom_scm_wb[cpu].entry)

			continue;

		flags |= qcom_scm_wb[cpu].flag;

	}



	/* No change in entry function */

	if (!flags)

		return 0;



	desc.args[0] = flags;

	desc.args[1] = virt_to_phys(entry);

	desc.arginfo = QCOM_SCM_ARGS(2);



	ret = qcom_scm_call(dev, &desc, NULL);

	if (!ret) {

		for_each_cpu(cpu, cpus)

			qcom_scm_wb[cpu].entry = entry;

	}



	return ret;

}



/**

 * qcom_scm_cpu_power_down() - Power down the cpu

 * @flags - Flags to flush cache

 *

 * This is an end point to power down cpu. If there was a pending interrupt,

 * the control would return from this function, otherwise, the cpu jumps to the

 * warm boot entry point set for this cpu upon reset.

 */

void __qcom_scm_cpu_power_down(struct device *dev, u32 flags)

{

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_BOOT,

		.cmd = QCOM_SCM_BOOT_TERMINATE_PC,

		.args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK,

		.arginfo = QCOM_SCM_ARGS(1),

	};



	qcom_scm_call_atomic(dev, &desc, NULL);

}



int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)

{

	int ret;
@@ -432,285 +258,6 @@ int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id) 
	return ret ? : res.result[0];

}



int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,

			u32 req_cnt, u32 *resp)

{

	int ret;

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_HDCP,

		.cmd = QCOM_SCM_HDCP_INVOKE,

	};

	struct qcom_scm_res res;



	if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)

		return -ERANGE;



	desc.args[0] = req[0].addr;

	desc.args[1] = req[0].val;

	desc.args[2] = req[1].addr;

	desc.args[3] = req[1].val;

	desc.args[4] = req[2].addr;

	desc.args[5] = req[2].val;

	desc.args[6] = req[3].addr;

	desc.args[7] = req[3].val;

	desc.args[8] = req[4].addr;

	desc.args[9] = req[4].val;

	desc.arginfo = QCOM_SCM_ARGS(10);



	ret = qcom_scm_call(dev, &desc, &res);

	*resp = res.result[0];



	return ret;

}



int __qcom_scm_ocmem_lock(struct device *dev, u32 id, u32 offset, u32 size,

			  u32 mode)

{

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_OCMEM,

		.cmd = QCOM_SCM_OCMEM_LOCK_CMD,

	};



	desc.args[0] = id;

	desc.args[1] = offset;

	desc.args[2] = size;

	desc.args[3] = mode;

	desc.arginfo = QCOM_SCM_ARGS(4);



	return qcom_scm_call(dev, &desc, NULL);

}



int __qcom_scm_ocmem_unlock(struct device *dev, u32 id, u32 offset, u32 size)

{

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_OCMEM,

		.cmd = QCOM_SCM_OCMEM_UNLOCK_CMD,

	};



	desc.args[0] = id;

	desc.args[1] = offset;

	desc.args[2] = size;

	desc.arginfo = QCOM_SCM_ARGS(3);



	return qcom_scm_call(dev, &desc, NULL);

}



void __qcom_scm_init(void)

{

}
 


bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)

{

	int ret;

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_PIL,

		.cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,

	};

	struct qcom_scm_res res;



	desc.args[0] = peripheral;

	desc.arginfo = QCOM_SCM_ARGS(1);



	ret = qcom_scm_call(dev, &desc, &res);



	return ret ? false : !!res.result[0];

}



int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,

			      dma_addr_t metadata_phys)

{

	int ret;

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_PIL,

		.cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,

	};

	struct qcom_scm_res res;



	desc.args[0] = peripheral;

	desc.args[1] = metadata_phys;

	desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW);



	ret = qcom_scm_call(dev, &desc, &res);



	return ret ? : res.result[0];

}



int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,

			      phys_addr_t addr, phys_addr_t size)

{

	int ret;

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_PIL,

		.cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,

	};

	struct qcom_scm_res res;



	desc.args[0] = peripheral;

	desc.args[1] = addr;

	desc.args[2] = size;

	desc.arginfo = QCOM_SCM_ARGS(3);



	ret = qcom_scm_call(dev, &desc, &res);



	return ret ? : res.result[0];

}



int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)

{

	int ret;

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_PIL,

		.cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,

	};

	struct qcom_scm_res res;



	desc.args[0] = peripheral;

	desc.arginfo = QCOM_SCM_ARGS(1);



	ret = qcom_scm_call(dev, &desc, &res);



	return ret ? : res.result[0];

}



int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral)

{

	int ret;

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_PIL,

		.cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,

	};

	struct qcom_scm_res res;



	desc.args[0] = peripheral;

	desc.arginfo = QCOM_SCM_ARGS(1);



	ret = qcom_scm_call(dev, &desc, &res);



	return ret ? : res.result[0];

}



int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)

{

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_PIL,

		.cmd = QCOM_SCM_PIL_PAS_MSS_RESET,

	};

	struct qcom_scm_res res;

	int ret;



	desc.args[0] = reset;

	desc.args[1] = 0;

	desc.arginfo = QCOM_SCM_ARGS(2);



	ret = qcom_scm_call(dev, &desc, &res);



	return ret ? : res.result[0];

}



int __qcom_scm_set_dload_mode(struct device *dev, bool enable)

{

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_BOOT,

		.cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE,

	};



	desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE;

	desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;

	desc.arginfo = QCOM_SCM_ARGS(2);



	return qcom_scm_call_atomic(dev, &desc, NULL);

}



int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)

{

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_BOOT,

		.cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,

	};

	struct qcom_scm_res res;

	int ret;



	desc.args[0] = state;

	desc.args[1] = id;



	ret = qcom_scm_call(dev, &desc, &res);



	return ret ? : res.result[0];

}



int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,

			  size_t mem_sz, phys_addr_t src, size_t src_sz,

			  phys_addr_t dest, size_t dest_sz)

{

	return -ENODEV;

}



int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,

			       u32 spare)

{

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_MP,

		.cmd = QCOM_SCM_MP_RESTORE_SEC_CFG,

	};

	struct qcom_scm_res res;

	int ret;



	desc.args[0] = device_id;

	desc.args[1] = spare;

	desc.arginfo = QCOM_SCM_ARGS(2);



	ret = qcom_scm_call(dev, &desc, &res);



	return ret ? : res.result[0];

}



int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,

				      size_t *size)

{

	return -ENODEV;

}



int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,

				      u32 spare)

{

	return -ENODEV;

}



int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,

			unsigned int *val)

{

	int ret;

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_IO,

		.cmd = QCOM_SCM_IO_READ,

	};

	struct qcom_scm_res res;



	desc.args[0] = addr;

	desc.arginfo = QCOM_SCM_ARGS(1);



	ret = qcom_scm_call_atomic(dev, &desc, &res);

	if (ret >= 0)

		*val = res.result[0];



	return ret < 0 ? ret : 0;

}



int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)

{

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_IO,

		.cmd = QCOM_SCM_IO_WRITE,

	};



	desc.args[0] = addr;

	desc.args[1] = val;

	desc.arginfo = QCOM_SCM_ARGS(2);



	return qcom_scm_call_atomic(dev, &desc, NULL);

}



int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool enable)

{

	return -ENODEV;

}

drivers/firmware/qcom_scm-64.c

+4 −430
Original line number Diff line number Diff line
@@ -16,52 +16,6 @@ 


#define SCM_SMC_FNID(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF))



#define MAX_QCOM_SCM_ARGS 10

#define MAX_QCOM_SCM_RETS 3



enum qcom_scm_arg_types {

	QCOM_SCM_VAL,

	QCOM_SCM_RO,

	QCOM_SCM_RW,

	QCOM_SCM_BUFVAL,

};



#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\

			   (((a) & 0x3) << 4) | \

			   (((b) & 0x3) << 6) | \

			   (((c) & 0x3) << 8) | \

			   (((d) & 0x3) << 10) | \

			   (((e) & 0x3) << 12) | \

			   (((f) & 0x3) << 14) | \

			   (((g) & 0x3) << 16) | \

			   (((h) & 0x3) << 18) | \

			   (((i) & 0x3) << 20) | \

			   (((j) & 0x3) << 22) | \

			   ((num) & 0xf))



#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)



/**

 * struct qcom_scm_desc

 * @arginfo:	Metadata describing the arguments in args[]

 * @args:	The array of arguments for the secure syscall

 */

struct qcom_scm_desc {

	u32 svc;

	u32 cmd;

	u32 arginfo;

	u64 args[MAX_QCOM_SCM_ARGS];

	u32 owner;

};



/**

 * struct qcom_scm_res

 * @result:	The values returned by the secure syscall

 */

struct qcom_scm_res {

	u64 result[MAX_QCOM_SCM_RETS];

};



/**

 * struct arm_smccc_args

 * @args:	The array of values used in registers in smc instruction
@@ -206,7 +160,7 @@ static int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc, 
 * Sends a command to the SCM and waits for the command to finish processing.

 * This should *only* be called in pre-emptible context.

 */

static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,

int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,

		  struct qcom_scm_res *res)

{

	might_sleep();
@@ -224,54 +178,12 @@ static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc, 
 * Sends a command to the SCM and waits for the command to finish processing.

 * This can be called in atomic context.

 */

static int qcom_scm_call_atomic(struct device *dev,

				const struct qcom_scm_desc *desc,

int qcom_scm_call_atomic(struct device *dev, const struct qcom_scm_desc *desc,

			 struct qcom_scm_res *res)

{

	return __scm_smc_call(dev, desc, res, true);

}



/**

 * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus

 * @entry: Entry point function for the cpus

 * @cpus: The cpumask of cpus that will use the entry point

 *

 * Set the cold boot address of the cpus. Any cpu outside the supported

 * range would be removed from the cpu present mask.

 */

int __qcom_scm_set_cold_boot_addr(struct device *dev, void *entry,

				  const cpumask_t *cpus)

{

	return -ENOTSUPP;

}



/**

 * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus

 * @dev: Device pointer

 * @entry: Entry point function for the cpus

 * @cpus: The cpumask of cpus that will use the entry point

 *

 * Set the Linux entry point for the SCM to transfer control to when coming

 * out of a power down. CPU power down may be executed on cpuidle or hotplug.

 */

int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,

				  const cpumask_t *cpus)

{

	return -ENOTSUPP;

}



/**

 * qcom_scm_cpu_power_down() - Power down the cpu

 * @flags - Flags to flush cache

 *

 * This is an end point to power down cpu. If there was a pending interrupt,

 * the control would return from this function, otherwise, the cpu jumps to the

 * warm boot entry point set for this cpu upon reset.

 */

void __qcom_scm_cpu_power_down(struct device *dev, u32 flags)

{

}



int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)

{

	int ret;
@@ -291,50 +203,6 @@ int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id) 
	return ret ? : res.result[0];

}



int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,

			u32 req_cnt, u32 *resp)

{

	int ret;

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_HDCP,

		.cmd = QCOM_SCM_HDCP_INVOKE,

		.owner = ARM_SMCCC_OWNER_SIP,

	};

	struct qcom_scm_res res;



	if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)

		return -ERANGE;



	desc.args[0] = req[0].addr;

	desc.args[1] = req[0].val;

	desc.args[2] = req[1].addr;

	desc.args[3] = req[1].val;

	desc.args[4] = req[2].addr;

	desc.args[5] = req[2].val;

	desc.args[6] = req[3].addr;

	desc.args[7] = req[3].val;

	desc.args[8] = req[4].addr;

	desc.args[9] = req[4].val;

	desc.arginfo = QCOM_SCM_ARGS(10);



	ret = qcom_scm_call(dev, &desc, &res);

	*resp = res.result[0];



	return ret;

}



int __qcom_scm_ocmem_lock(struct device *dev, uint32_t id, uint32_t offset,

			  uint32_t size, uint32_t mode)

{

	return -ENOTSUPP;

}



int __qcom_scm_ocmem_unlock(struct device *dev, uint32_t id, uint32_t offset,

			    uint32_t size)

{

	return -ENOTSUPP;

}



void __qcom_scm_init(void)

{

	struct qcom_scm_desc desc = {
@@ -366,297 +234,3 @@ void __qcom_scm_init(void) 
out:

	pr_info("QCOM SCM SMC Convention: %lld\n", qcom_smccc_convention);

}
 


bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)

{

	int ret;

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_PIL,

		.cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,

		.owner = ARM_SMCCC_OWNER_SIP,

	};

	struct qcom_scm_res res;



	desc.args[0] = peripheral;

	desc.arginfo = QCOM_SCM_ARGS(1);



	ret = qcom_scm_call(dev, &desc, &res);



	return ret ? false : !!res.result[0];

}



int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,

			      dma_addr_t metadata_phys)

{

	int ret;

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_PIL,

		.cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,

		.owner = ARM_SMCCC_OWNER_SIP,

	};

	struct qcom_scm_res res;



	desc.args[0] = peripheral;

	desc.args[1] = metadata_phys;

	desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW);



	ret = qcom_scm_call(dev, &desc, &res);



	return ret ? : res.result[0];

}



int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,

			      phys_addr_t addr, phys_addr_t size)

{

	int ret;

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_PIL,

		.cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,

		.owner = ARM_SMCCC_OWNER_SIP,

	};

	struct qcom_scm_res res;



	desc.args[0] = peripheral;

	desc.args[1] = addr;

	desc.args[2] = size;

	desc.arginfo = QCOM_SCM_ARGS(3);



	ret = qcom_scm_call(dev, &desc, &res);



	return ret ? : res.result[0];

}



int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)

{

	int ret;

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_PIL,

		.cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,

		.owner = ARM_SMCCC_OWNER_SIP,

	};

	struct qcom_scm_res res;



	desc.args[0] = peripheral;

	desc.arginfo = QCOM_SCM_ARGS(1);



	ret = qcom_scm_call(dev, &desc, &res);



	return ret ? : res.result[0];

}



int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral)

{

	int ret;

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_PIL,

		.cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,

		.owner = ARM_SMCCC_OWNER_SIP,

	};

	struct qcom_scm_res res;



	desc.args[0] = peripheral;

	desc.arginfo = QCOM_SCM_ARGS(1);



	ret = qcom_scm_call(dev, &desc, &res);



	return ret ? : res.result[0];

}



int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)

{

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_PIL,

		.cmd = QCOM_SCM_PIL_PAS_MSS_RESET,

		.owner = ARM_SMCCC_OWNER_SIP,

	};

	struct qcom_scm_res res;

	int ret;



	desc.args[0] = reset;

	desc.args[1] = 0;

	desc.arginfo = QCOM_SCM_ARGS(2);



	ret = qcom_scm_call(dev, &desc, &res);



	return ret ? : res.result[0];

}



int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)

{

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_BOOT,

		.cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,

		.owner = ARM_SMCCC_OWNER_SIP,

	};

	struct qcom_scm_res res;

	int ret;



	desc.args[0] = state;

	desc.args[1] = id;

	desc.arginfo = QCOM_SCM_ARGS(2);



	ret = qcom_scm_call(dev, &desc, &res);



	return ret ? : res.result[0];

}



int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,

			  size_t mem_sz, phys_addr_t src, size_t src_sz,

			  phys_addr_t dest, size_t dest_sz)

{

	int ret;

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_MP,

		.cmd = QCOM_SCM_MP_ASSIGN,

		.owner = ARM_SMCCC_OWNER_SIP,

	};

	struct qcom_scm_res res;



	desc.args[0] = mem_region;

	desc.args[1] = mem_sz;

	desc.args[2] = src;

	desc.args[3] = src_sz;

	desc.args[4] = dest;

	desc.args[5] = dest_sz;

	desc.args[6] = 0;



	desc.arginfo = QCOM_SCM_ARGS(7, QCOM_SCM_RO, QCOM_SCM_VAL,

				     QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO,

				     QCOM_SCM_VAL, QCOM_SCM_VAL);



	ret = qcom_scm_call(dev, &desc, &res);



	return ret ? : res.result[0];

}



int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare)

{

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_MP,

		.cmd = QCOM_SCM_MP_RESTORE_SEC_CFG,

		.owner = ARM_SMCCC_OWNER_SIP,

	};

	struct qcom_scm_res res;

	int ret;



	desc.args[0] = device_id;

	desc.args[1] = spare;

	desc.arginfo = QCOM_SCM_ARGS(2);



	ret = qcom_scm_call(dev, &desc, &res);



	return ret ? : res.result[0];

}



int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,

				      size_t *size)

{

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_MP,

		.cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE,

		.owner = ARM_SMCCC_OWNER_SIP,

	};

	struct qcom_scm_res res;

	int ret;



	desc.args[0] = spare;

	desc.arginfo = QCOM_SCM_ARGS(1);



	ret = qcom_scm_call(dev, &desc, &res);



	if (size)

		*size = res.result[0];



	return ret ? : res.result[1];

}



int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,

				      u32 spare)

{

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_MP,

		.cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT,

		.owner = ARM_SMCCC_OWNER_SIP,

	};

	int ret;



	desc.args[0] = addr;

	desc.args[1] = size;

	desc.args[2] = spare;

	desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL,

				     QCOM_SCM_VAL);



	ret = qcom_scm_call(dev, &desc, NULL);



	/* the pg table has been initialized already, ignore the error */

	if (ret == -EPERM)

		ret = 0;



	return ret;

}



int __qcom_scm_set_dload_mode(struct device *dev, bool enable)

{

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_BOOT,

		.cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE,

		.owner = ARM_SMCCC_OWNER_SIP,

	};



	desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE;

	desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;

	desc.arginfo = QCOM_SCM_ARGS(2);



	return qcom_scm_call(dev, &desc, NULL);

}



int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,

			unsigned int *val)

{

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_IO,

		.cmd = QCOM_SCM_IO_READ,

		.owner = ARM_SMCCC_OWNER_SIP,

	};

	struct qcom_scm_res res;

	int ret;



	desc.args[0] = addr;

	desc.arginfo = QCOM_SCM_ARGS(1);



	ret = qcom_scm_call(dev, &desc, &res);

	if (ret >= 0)

		*val = res.result[0];



	return ret < 0 ? ret : 0;

}



int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)

{

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_IO,

		.cmd = QCOM_SCM_IO_WRITE,

		.owner = ARM_SMCCC_OWNER_SIP,

	};



	desc.args[0] = addr;

	desc.args[1] = val;

	desc.arginfo = QCOM_SCM_ARGS(2);



	return qcom_scm_call(dev, &desc, NULL);

}



int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool en)

{

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_SMMU_PROGRAM,

		.cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1,

		.owner = ARM_SMCCC_OWNER_SIP,

	};



	desc.args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL;

	desc.args[1] = en;

	desc.arginfo = QCOM_SCM_ARGS(2);



	return qcom_scm_call_atomic(dev, &desc, NULL);

}

drivers/firmware/qcom_scm.c

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drivers/firmware/qcom_scm.h

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