Commit 5784e91a authored by Lorenzo Bianconi's avatar Lorenzo Bianconi Committed by Felix Fietkau
Browse files

mt76: mt7615: introduce mt7615_init_mac_chain routine 



Introduce mt7615_init_mac_chain routine to configure per band mac
register since new devices (e.g. mt7663e) do not support dbdc

Signed-off-by: default avatarLorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent b3d95f09

drivers/net/wireless/mediatek/mt76/mt7615/init.c

+62 −56
Original line number Diff line number Diff line
@@ -18,74 +18,48 @@ static void mt7615_phy_init(struct mt7615_dev *dev) 
	mt76_set(dev, MT_WF_PHY_WF2_RFCTRL0(1), MT_WF_PHY_WF2_RFCTRL0_LPBCN_EN);

}



static void mt7615_mac_init(struct mt7615_dev *dev)

static void

mt7615_init_mac_chain(struct mt7615_dev *dev, int chain)

{

	u32 val, mask, set;

	int i;



	if (!chain)

		val = MT_CFG_CCR_MAC_D0_1X_GC_EN | MT_CFG_CCR_MAC_D0_2X_GC_EN;

	else

		val = MT_CFG_CCR_MAC_D1_1X_GC_EN | MT_CFG_CCR_MAC_D1_2X_GC_EN;



	/* enable band 0/1 clk */

	mt76_set(dev, MT_CFG_CCR,

		 MT_CFG_CCR_MAC_D0_1X_GC_EN | MT_CFG_CCR_MAC_D0_2X_GC_EN |

		 MT_CFG_CCR_MAC_D1_1X_GC_EN | MT_CFG_CCR_MAC_D1_2X_GC_EN);

	mt76_set(dev, MT_CFG_CCR, val);



	val = mt76_rmw(dev, MT_TMAC_TRCR(0),

	mt76_rmw(dev, MT_TMAC_TRCR(chain),

		 MT_TMAC_TRCR_CCA_SEL | MT_TMAC_TRCR_SEC_CCA_SEL,

		 FIELD_PREP(MT_TMAC_TRCR_CCA_SEL, 2) |

		 FIELD_PREP(MT_TMAC_TRCR_SEC_CCA_SEL, 0));

	mt76_wr(dev, MT_TMAC_TRCR(1), val);



	val = MT_AGG_ACR_PKT_TIME_EN | MT_AGG_ACR_NO_BA_AR_RULE |

	mt76_wr(dev, MT_AGG_ACR(chain),

		MT_AGG_ACR_PKT_TIME_EN | MT_AGG_ACR_NO_BA_AR_RULE |

		FIELD_PREP(MT_AGG_ACR_CFEND_RATE, MT7615_CFEND_RATE_DEFAULT) |

	      FIELD_PREP(MT_AGG_ACR_BAR_RATE, MT7615_BAR_RATE_DEFAULT);

	mt76_wr(dev, MT_AGG_ACR(0), val);

	mt76_wr(dev, MT_AGG_ACR(1), val);



	mt76_rmw_field(dev, MT_TMAC_CTCR0,

		       MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f);

	mt76_rmw_field(dev, MT_TMAC_CTCR0,

		       MT_TMAC_CTCR0_INS_DDLMT_DENSITY, 0x3);

	mt76_rmw(dev, MT_TMAC_CTCR0,

		 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN |

		 MT_TMAC_CTCR0_INS_DDLMT_EN,

		 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN |

		 MT_TMAC_CTCR0_INS_DDLMT_EN);

		FIELD_PREP(MT_AGG_ACR_BAR_RATE, MT7615_BAR_RATE_DEFAULT));



	mt7615_mcu_set_rts_thresh(&dev->phy, 0x92b);

	mt7615_mac_set_scs(dev, true);



	mt76_rmw(dev, MT_AGG_SCR, MT_AGG_SCR_NLNAV_MID_PTEC_DIS,

		 MT_AGG_SCR_NLNAV_MID_PTEC_DIS);



	mt76_wr(dev, MT_DMA_DCR0, MT_DMA_DCR0_RX_VEC_DROP |

		FIELD_PREP(MT_DMA_DCR0_MAX_RX_LEN, 3072));



	val = FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), 7) |

	mt76_wr(dev, MT_AGG_ARUCR(chain),

		FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), 7) |

		FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), 2) |

		FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), 2) |

		FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), 2) |

		FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), 1) |

		FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), 1) |

		FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), 1) |

	      FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), 1);

	mt76_wr(dev, MT_AGG_ARUCR(0), val);

	mt76_wr(dev, MT_AGG_ARUCR(1), val);

		FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), 1));



	val = FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), MT7615_RATE_RETRY - 1) |

	mt76_wr(dev, MT_AGG_ARDCR(chain),

		FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), MT7615_RATE_RETRY - 1) |

		FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), MT7615_RATE_RETRY - 1) |

		FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), MT7615_RATE_RETRY - 1) |

		FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), MT7615_RATE_RETRY - 1) |

		FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), MT7615_RATE_RETRY - 1) |

		FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), MT7615_RATE_RETRY - 1) |

		FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), MT7615_RATE_RETRY - 1) |

	      FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), MT7615_RATE_RETRY - 1);

	mt76_wr(dev, MT_AGG_ARDCR(0), val);

	mt76_wr(dev, MT_AGG_ARDCR(1), val);



	mt76_wr(dev, MT_AGG_ARCR,

		(FIELD_PREP(MT_AGG_ARCR_RTS_RATE_THR, 2) |

		 MT_AGG_ARCR_RATE_DOWN_RATIO_EN |

		 FIELD_PREP(MT_AGG_ARCR_RATE_DOWN_RATIO, 1) |

		 FIELD_PREP(MT_AGG_ARCR_RATE_UP_EXTRA_TH, 4)));

		FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), MT7615_RATE_RETRY - 1));



	mask = MT_DMA_RCFR0_MCU_RX_MGMT |

	       MT_DMA_RCFR0_MCU_RX_CTL_NON_BAR |
@@ -95,8 +69,40 @@ static void mt7615_mac_init(struct mt7615_dev *dev) 
	       MT_DMA_RCFR0_RX_DROPPED_MCAST;

	set = FIELD_PREP(MT_DMA_RCFR0_RX_DROPPED_UCAST, 2) |

	      FIELD_PREP(MT_DMA_RCFR0_RX_DROPPED_MCAST, 2);

	mt76_rmw(dev, MT_DMA_RCFR0(0), mask, set);

	mt76_rmw(dev, MT_DMA_RCFR0(1), mask, set);

	mt76_rmw(dev, MT_DMA_RCFR0(chain), mask, set);

}



static void mt7615_mac_init(struct mt7615_dev *dev)

{

	int i;



	mt7615_init_mac_chain(dev, 0);

	mt7615_init_mac_chain(dev, 1);



	mt76_rmw_field(dev, MT_TMAC_CTCR0,

		       MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f);

	mt76_rmw_field(dev, MT_TMAC_CTCR0,

		       MT_TMAC_CTCR0_INS_DDLMT_DENSITY, 0x3);

	mt76_rmw(dev, MT_TMAC_CTCR0,

		 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN |

		 MT_TMAC_CTCR0_INS_DDLMT_EN,

		 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN |

		 MT_TMAC_CTCR0_INS_DDLMT_EN);



	mt7615_mcu_set_rts_thresh(&dev->phy, 0x92b);

	mt7615_mac_set_scs(dev, true);



	mt76_rmw(dev, MT_AGG_SCR, MT_AGG_SCR_NLNAV_MID_PTEC_DIS,

		 MT_AGG_SCR_NLNAV_MID_PTEC_DIS);



	mt76_wr(dev, MT_AGG_ARCR,

		FIELD_PREP(MT_AGG_ARCR_RTS_RATE_THR, 2) |

		MT_AGG_ARCR_RATE_DOWN_RATIO_EN |

		FIELD_PREP(MT_AGG_ARCR_RATE_DOWN_RATIO, 1) |

		FIELD_PREP(MT_AGG_ARCR_RATE_UP_EXTRA_TH, 4));



	mt76_wr(dev, MT_DMA_DCR0, MT_DMA_DCR0_RX_VEC_DROP |

		FIELD_PREP(MT_DMA_DCR0_MAX_RX_LEN, 3072));



	for (i = 0; i < MT7615_WTBL_SIZE; i++)

		mt7615_mac_wtbl_update(dev, i,

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