Commit 577dd5de authored by Robin Murphy's avatar Robin Murphy Committed by Sudeep Holla
Browse files

arm64: dts: juno: add GPU subsystem 



Since we now have bindings for Mali Midgard GPUs, let's use them to
describe Juno's GPU subsystem, if only because we can. Juno sports a
Mali-T624 integrated behind an MMU-400 (as a gesture towards
virtualisation), in their own dedicated power domain with DVFS
controlled by the SCP.

CC: Liviu Dudau <liviu.dudau@arm.com>
CC: Sudeep Holla <sudeep.holla@arm.com>
CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: default avatarRobin Murphy <robin.murphy@arm.com>
Acked-by: default avatarLiviu Dudau <liviu.dudau@arm.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
parent 54ecb8f7

Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml

+4 −1
Original line number Diff line number Diff line
@@ -22,6 +22,10 @@ properties: 
          - enum:

             - amlogic,meson-gxm-mali

          - const: arm,mali-t820

      - items:

          - enum:

             - arm,juno-mali

          - const: arm,mali-t624

      - items:

          - enum:

             - rockchip,rk3288-mali
@@ -39,7 +43,6 @@ properties: 
             - samsung,exynos5433-mali

          - const: arm,mali-t760



          # "arm,mali-t624"

          # "arm,mali-t628"

          # "arm,mali-t830"

          # "arm,mali-t880"

arch/arm64/boot/dts/arm/juno-base.dtsi

+27 −0
Original line number Diff line number Diff line
@@ -35,6 +35,18 @@ 
		clock-names = "apb_pclk";

	};



	smmu_gpu: iommu@2b400000 {

		compatible = "arm,mmu-400", "arm,smmu-v1";

		reg = <0x0 0x2b400000 0x0 0x10000>;

		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;

		#iommu-cells = <1>;

		#global-interrupts = <1>;

		power-domains = <&scpi_devpd 1>;

		dma-coherent;

		status = "disabled";

	};



	smmu_pcie: iommu@2b500000 {

		compatible = "arm,mmu-401", "arm,smmu-v1";

		reg = <0x0 0x2b500000 0x0 0x10000>;
@@ -487,6 +499,21 @@ 
		};

	};



	gpu: gpu@2d000000 {

		compatible = "arm,juno-mali", "arm,mali-t624";

		reg = <0 0x2d000000 0 0x10000>;

		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "gpu", "job", "mmu";

		clocks = <&scpi_dvfs 2>;

		power-domains = <&scpi_devpd 1>;

		dma-coherent;

		/* The SMMU is only really of interest to bare-metal hypervisors */

		/* iommus = <&smmu_gpu 0>; */

		status = "disabled";

	};



	sram: sram@2e000000 {

		compatible = "arm,juno-sram-ns", "mmio-sram";

		reg = <0x0 0x2e000000 0x0 0x8000>;

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