Commit 57701171 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'bnxt_en-Update-for-net-next' 



Michael Chan says:

====================
bnxt_en: Update for net-next.

This series includes the usual firmware spec. update, a PCI ID addition,
enhancements for VF trust, MDIO read/write for external PHY, and
fixing the return code when TC flow offload fails.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 4509de14 b2d69122

drivers/net/ethernet/broadcom/bnxt/bnxt.c

+75 −3
Original line number Diff line number Diff line 
/* Broadcom NetXtreme-C/E network driver.

 *

 * Copyright (c) 2014-2016 Broadcom Corporation

 * Copyright (c) 2016-2018 Broadcom Limited

 * Copyright (c) 2016-2019 Broadcom Limited

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by
@@ -31,6 +31,7 @@ 
#include <asm/page.h>

#include <linux/time.h>

#include <linux/mii.h>

#include <linux/mdio.h>

#include <linux/if.h>

#include <linux/if_vlan.h>

#include <linux/if_bridge.h>
@@ -112,6 +113,7 @@ enum board_idx { 
	BCM57454,

	BCM5745x_NPAR,

	BCM57508,

	BCM57504,

	BCM58802,

	BCM58804,

	BCM58808,
@@ -155,6 +157,7 @@ static const struct { 
	[BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },

	[BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },

	[BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },

	[BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },

	[BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },

	[BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },

	[BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
@@ -201,6 +204,7 @@ static const struct pci_device_id bnxt_pci_tbl[] = { 
	{ PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },

	{ PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },

	{ PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },

	{ PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },

	{ PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },

	{ PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },

#ifdef CONFIG_BNXT_SRIOV
@@ -6680,6 +6684,10 @@ static int bnxt_hwrm_ver_get(struct bnxt *bp) 
	    VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED)

		bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE;



	if (dev_caps_cfg &

	    VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)

		bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF;



hwrm_ver_get_exit:

	mutex_unlock(&bp->hwrm_cmd_lock);

	return rc;
@@ -8614,24 +8622,88 @@ static int bnxt_close(struct net_device *dev) 
	return 0;

}



static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg,

				   u16 *val)

{

	struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr;

	struct hwrm_port_phy_mdio_read_input req = {0};

	int rc;



	if (bp->hwrm_spec_code < 0x10a00)

		return -EOPNOTSUPP;



	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1);

	req.port_id = cpu_to_le16(bp->pf.port_id);

	req.phy_addr = phy_addr;

	req.reg_addr = cpu_to_le16(reg & 0x1f);

	if (bp->link_info.support_speeds & BNXT_LINK_SPEED_MSK_10GB) {

		req.cl45_mdio = 1;

		req.phy_addr = mdio_phy_id_prtad(phy_addr);

		req.dev_addr = mdio_phy_id_devad(phy_addr);

		req.reg_addr = cpu_to_le16(reg);

	}



	mutex_lock(&bp->hwrm_cmd_lock);

	rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);

	if (!rc)

		*val = le16_to_cpu(resp->reg_data);

	mutex_unlock(&bp->hwrm_cmd_lock);

	return rc;

}



static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg,

				    u16 val)

{

	struct hwrm_port_phy_mdio_write_input req = {0};



	if (bp->hwrm_spec_code < 0x10a00)

		return -EOPNOTSUPP;



	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1);

	req.port_id = cpu_to_le16(bp->pf.port_id);

	req.phy_addr = phy_addr;

	req.reg_addr = cpu_to_le16(reg & 0x1f);

	if (bp->link_info.support_speeds & BNXT_LINK_SPEED_MSK_10GB) {

		req.cl45_mdio = 1;

		req.phy_addr = mdio_phy_id_prtad(phy_addr);

		req.dev_addr = mdio_phy_id_devad(phy_addr);

		req.reg_addr = cpu_to_le16(reg);

	}

	req.reg_data = cpu_to_le16(val);



	return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);

}



/* rtnl_lock held */

static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)

{

	struct mii_ioctl_data *mdio = if_mii(ifr);

	struct bnxt *bp = netdev_priv(dev);

	int rc;



	switch (cmd) {

	case SIOCGMIIPHY:

		mdio->phy_id = bp->link_info.phy_addr;



		/* fallthru */

	case SIOCGMIIREG: {

		u16 mii_regval = 0;



		if (!netif_running(dev))

			return -EAGAIN;



		return 0;

		rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,

					     &mii_regval);

		mdio->val_out = mii_regval;

		return rc;

	}



	case SIOCSMIIREG:

		if (!netif_running(dev))

			return -EAGAIN;



		return 0;

		return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,

						mdio->val_in);



	default:

		/* do nothing */

drivers/net/ethernet/broadcom/bnxt/bnxt.h

+2 −0
Original line number Diff line number Diff line
@@ -945,6 +945,7 @@ struct bnxt_vf_info { 
					 * stored by PF.

					 */

	u16	vlan;

	u16	func_qcfg_flags;

	u32	flags;

#define BNXT_VF_QOS		0x1

#define BNXT_VF_SPOOFCHK	0x2
@@ -1478,6 +1479,7 @@ struct bnxt { 
	#define BNXT_FW_CAP_IF_CHANGE			0x00000010

	#define BNXT_FW_CAP_KONG_MB_CHNL		0x00000080

	#define BNXT_FW_CAP_OVS_64BIT_HANDLE		0x00000400

	#define BNXT_FW_CAP_TRUSTED_VF			0x00000800



#define BNXT_NEW_RM(bp)		((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)

	u32			hwrm_spec_code;

drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h

+177 −19
Original line number Diff line number Diff line 
/* Broadcom NetXtreme-C/E network driver.

 *

 * Copyright (c) 2014-2016 Broadcom Corporation

 * Copyright (c) 2016-2018 Broadcom Limited

 * Copyright (c) 2016-2019 Broadcom Limited

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by
@@ -98,6 +98,7 @@ struct hwrm_short_input { 
struct cmd_nums {

	__le16	req_type;

	#define HWRM_VER_GET                              0x0UL

	#define HWRM_ERROR_RECOVERY_QCFG                  0xcUL

	#define HWRM_FUNC_DRV_IF_CHANGE                   0xdUL

	#define HWRM_FUNC_BUF_UNRGTR                      0xeUL

	#define HWRM_FUNC_VF_CFG                          0xfUL
@@ -221,6 +222,7 @@ struct cmd_nums { 
	#define HWRM_CFA_METER_PROFILE_CFG                0xf7UL

	#define HWRM_CFA_METER_INSTANCE_ALLOC             0xf8UL

	#define HWRM_CFA_METER_INSTANCE_FREE              0xf9UL

	#define HWRM_CFA_METER_INSTANCE_CFG               0xfaUL

	#define HWRM_CFA_VFR_ALLOC                        0xfdUL

	#define HWRM_CFA_VFR_FREE                         0xfeUL

	#define HWRM_CFA_VF_PAIR_ALLOC                    0x100UL
@@ -269,6 +271,7 @@ struct cmd_nums { 
	#define HWRM_ENGINE_CKV_FLUSH                     0x133UL

	#define HWRM_ENGINE_CKV_RNG_GET                   0x134UL

	#define HWRM_ENGINE_CKV_KEY_GEN                   0x135UL

	#define HWRM_ENGINE_CKV_KEY_LABEL_CFG             0x136UL

	#define HWRM_ENGINE_QG_CONFIG_QUERY               0x13cUL

	#define HWRM_ENGINE_QG_QUERY                      0x13dUL

	#define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL
@@ -296,6 +299,7 @@ struct cmd_nums { 
	#define HWRM_ENGINE_NQ_ALLOC                      0x162UL

	#define HWRM_ENGINE_NQ_FREE                       0x163UL

	#define HWRM_ENGINE_ON_DIE_RQE_CREDITS            0x164UL

	#define HWRM_ENGINE_FUNC_QCFG                     0x165UL

	#define HWRM_FUNC_RESOURCE_QCAPS                  0x190UL

	#define HWRM_FUNC_VF_RESOURCE_CFG                 0x191UL

	#define HWRM_FUNC_BACKING_STORE_QCAPS             0x192UL
@@ -379,15 +383,15 @@ struct hwrm_err_output { 
};

#define HWRM_NA_SIGNATURE ((__le32)(-1))

#define HWRM_MAX_REQ_LEN 128

#define HWRM_MAX_RESP_LEN 280

#define HWRM_MAX_RESP_LEN 704

#define HW_HASH_INDEX_SIZE 0x80

#define HW_HASH_KEY_SIZE 40

#define HWRM_RESP_VALID_KEY 1

#define HWRM_VERSION_MAJOR 1

#define HWRM_VERSION_MINOR 10

#define HWRM_VERSION_UPDATE 0

#define HWRM_VERSION_RSVD 35

#define HWRM_VERSION_STR "1.10.0.35"

#define HWRM_VERSION_RSVD 47

#define HWRM_VERSION_STR "1.10.0.47"



/* hwrm_ver_get_input (size:192b/24B) */

struct hwrm_ver_get_input {
@@ -580,6 +584,7 @@ struct hwrm_async_event_cmpl { 
	#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE      0x6UL

	#define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE        0x7UL

	#define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY               0x8UL

	#define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY             0x9UL

	#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD           0x10UL

	#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD             0x11UL

	#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT        0x12UL
@@ -595,6 +600,9 @@ struct hwrm_async_event_cmpl { 
	#define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION         0x37UL

	#define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ        0x38UL

	#define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE       0x39UL

	#define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE     0x3aUL

	#define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE            0x3bUL

	#define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE             0x3cUL

	#define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG               0xfeUL

	#define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR                 0xffUL

	#define ASYNC_EVENT_CMPL_EVENT_ID_LAST                      ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
@@ -724,6 +732,30 @@ struct hwrm_async_event_cmpl_reset_notify { 
	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT            16

};



/* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */

struct hwrm_async_event_cmpl_error_recovery {

	__le16	type;

	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK            0x3fUL

	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT             0

	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT  0x2eUL

	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT

	__le16	event_id;

	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL

	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST          ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY

	__le32	event_data2;

	u8	opaque_v;

	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V          0x1UL

	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL

	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1

	u8	timestamp_lo;

	__le16	timestamp_hi;

	__le32	event_data1;

	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK                 0xffUL

	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT                  0

	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC           0x1UL

	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED      0x2UL

};



/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */

struct hwrm_async_event_cmpl_vf_cfg_change {

	__le16	type;
@@ -1014,6 +1046,7 @@ struct hwrm_func_qcaps_output { 
	#define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE                   0x100000UL

	#define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC           0x200000UL

	#define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE               0x400000UL

	#define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE          0x800000UL

	u8	mac_address[6];

	__le16	max_rsscos_ctx;

	__le16	max_cmpl_rings;
@@ -1185,6 +1218,7 @@ struct hwrm_func_cfg_input { 
	#define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE              0x200000UL

	#define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC          0x400000UL

	#define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST                 0x800000UL

	#define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE             0x1000000UL

	__le32	enables;

	#define FUNC_CFG_REQ_ENABLES_MTU                     0x1UL

	#define FUNC_CFG_REQ_ENABLES_MRU                     0x2UL
@@ -1390,6 +1424,7 @@ struct hwrm_func_drv_rgtr_input { 
	#define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE             0x4UL

	#define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE     0x8UL

	#define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT          0x10UL

	#define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT     0x20UL

	__le32	enables;

	#define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE             0x1UL

	#define FUNC_DRV_RGTR_REQ_ENABLES_VER                 0x2UL
@@ -2024,6 +2059,89 @@ struct hwrm_func_backing_store_cfg_output { 
	u8	valid;

};



/* hwrm_error_recovery_qcfg_input (size:192b/24B) */

struct hwrm_error_recovery_qcfg_input {

	__le16	req_type;

	__le16	cmpl_ring;

	__le16	seq_id;

	__le16	target_id;

	__le64	resp_addr;

	u8	unused_0[8];

};



/* hwrm_error_recovery_qcfg_output (size:1664b/208B) */

struct hwrm_error_recovery_qcfg_output {

	__le16	error_code;

	__le16	req_type;

	__le16	seq_id;

	__le16	resp_len;

	__le32	flags;

	#define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST       0x1UL

	#define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU     0x2UL

	__le32	driver_polling_freq;

	__le32	master_func_wait_period;

	__le32	normal_func_wait_period;

	__le32	master_func_wait_period_after_reset;

	__le32	max_bailout_time_after_reset;

	__le32	fw_health_status_reg;

	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK    0x3UL

	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT     0

	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG  0x0UL

	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC       0x1UL

	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0      0x2UL

	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1      0x3UL

	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1

	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK          0xfffffffcUL

	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT           2

	__le32	fw_heartbeat_reg;

	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK    0x3UL

	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT     0

	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG  0x0UL

	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC       0x1UL

	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0      0x2UL

	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1      0x3UL

	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1

	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK          0xfffffffcUL

	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT           2

	__le32	fw_reset_cnt_reg;

	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK    0x3UL

	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT     0

	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG  0x0UL

	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC       0x1UL

	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0      0x2UL

	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1      0x3UL

	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1

	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK          0xfffffffcUL

	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT           2

	__le32	reset_inprogress_reg;

	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK    0x3UL

	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT     0

	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG  0x0UL

	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC       0x1UL

	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0      0x2UL

	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1      0x3UL

	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1

	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK          0xfffffffcUL

	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT           2

	__le32	reset_inprogress_reg_mask;

	u8	unused_0[3];

	u8	reg_array_cnt;

	__le32	reset_reg[16];

	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK    0x3UL

	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT     0

	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG  0x0UL

	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC       0x1UL

	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0      0x2UL

	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1      0x3UL

	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1

	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK          0xfffffffcUL

	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT           2

	__le32	reset_reg_val[16];

	u8	delay_after_reset[16];

	u8	unused_1[7];

	u8	valid;

};



/* hwrm_func_drv_if_change_input (size:192b/24B) */

struct hwrm_func_drv_if_change_input {

	__le16	req_type;
@@ -2955,6 +3073,7 @@ struct hwrm_port_phy_qcaps_output { 
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB       0x800UL

	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD      0x1000UL

	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB        0x2000UL

	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_200GB       0x4000UL

	__le16	supported_speeds_auto_mode;

	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD     0x1UL

	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB       0x2UL
@@ -2970,6 +3089,7 @@ struct hwrm_port_phy_qcaps_output { 
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB       0x800UL

	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD      0x1000UL

	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB        0x2000UL

	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_200GB       0x4000UL

	__le16	supported_speeds_eee_mode;

	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1     0x1UL

	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB     0x2UL
@@ -4919,6 +5039,35 @@ struct hwrm_ring_free_output { 
	u8	valid;

};



/* hwrm_ring_reset_input (size:192b/24B) */

struct hwrm_ring_reset_input {

	__le16	req_type;

	__le16	cmpl_ring;

	__le16	seq_id;

	__le16	target_id;

	__le64	resp_addr;

	u8	ring_type;

	#define RING_RESET_REQ_RING_TYPE_L2_CMPL   0x0UL

	#define RING_RESET_REQ_RING_TYPE_TX        0x1UL

	#define RING_RESET_REQ_RING_TYPE_RX        0x2UL

	#define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL

	#define RING_RESET_REQ_RING_TYPE_LAST     RING_RESET_REQ_RING_TYPE_ROCE_CMPL

	u8	unused_0;

	__le16	ring_id;

	u8	unused_1[4];

};



/* hwrm_ring_reset_output (size:128b/16B) */

struct hwrm_ring_reset_output {

	__le16	error_code;

	__le16	req_type;

	__le16	seq_id;

	__le16	resp_len;

	u8	unused_0[4];

	u8	consumer_idx[3];

	u8	valid;

};



/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */

struct hwrm_ring_aggint_qcaps_input {

	__le16	req_type;
@@ -5446,6 +5595,7 @@ struct hwrm_cfa_encap_record_alloc_input { 
	__le64	resp_addr;

	__le32	flags;

	#define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK     0x1UL

	#define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL     0x2UL

	u8	encap_type;

	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN        0x1UL

	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE        0x2UL
@@ -5458,7 +5608,8 @@ struct hwrm_cfa_encap_record_alloc_input { 
	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4     0x9UL

	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1     0xaUL

	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE     0xbUL

	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST    CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE

	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL

	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST        CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6

	u8	unused_0[3];

	__le32	encap_data[20];

};
@@ -5506,6 +5657,7 @@ struct hwrm_cfa_ntuple_filter_alloc_input { 
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK     0x1UL

	#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP         0x2UL

	#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER        0x4UL

	#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID     0x8UL

	__le32	enables;

	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID         0x1UL

	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE            0x2UL
@@ -5627,7 +5779,8 @@ struct hwrm_cfa_ntuple_filter_cfg_input { 
	#define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID                0x1UL

	#define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID        0x2UL

	#define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID     0x4UL

	u8	unused_0[4];

	__le32	flags;

	#define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID     0x1UL

	__le64	ntuple_filter_id;

	__le32	new_dst_id;

	__le32	new_mirror_vnic_id;
@@ -5892,13 +6045,15 @@ struct hwrm_cfa_flow_info_input { 
	__le64	ext_flow_handle;

};



/* hwrm_cfa_flow_info_output (size:448b/56B) */

/* hwrm_cfa_flow_info_output (size:5632b/704B) */

struct hwrm_cfa_flow_info_output {

	__le16	error_code;

	__le16	req_type;

	__le16	seq_id;

	__le16	resp_len;

	u8	flags;

	#define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX     0x1UL

	#define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX     0x2UL

	u8	profile;

	__le16	src_fid;

	__le16	dst_fid;
@@ -5910,7 +6065,10 @@ struct hwrm_cfa_flow_info_output { 
	__le16	flow_handle;

	__le32	tunnel_handle;

	__le16	flow_timer;

	u8	unused_0[5];

	u8	unused_0[6];

	__le32	flow_key_data[130];

	__le32	flow_action_info[30];

	u8	unused_1[7];

	u8	valid;

};

drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c

+54 −4
Original line number Diff line number Diff line
@@ -121,6 +121,54 @@ int bnxt_set_vf_spoofchk(struct net_device *dev, int vf_id, bool setting) 
	return rc;

}



static int bnxt_hwrm_func_qcfg_flags(struct bnxt *bp, struct bnxt_vf_info *vf)

{

	struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;

	struct hwrm_func_qcfg_input req = {0};

	int rc;



	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);

	req.fid = cpu_to_le16(vf->fw_fid);

	mutex_lock(&bp->hwrm_cmd_lock);

	rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);

	if (rc) {

		mutex_unlock(&bp->hwrm_cmd_lock);

		return -EIO;

	}

	vf->func_qcfg_flags = le16_to_cpu(resp->flags);

	mutex_unlock(&bp->hwrm_cmd_lock);

	return 0;

}



static bool bnxt_is_trusted_vf(struct bnxt *bp, struct bnxt_vf_info *vf)

{

	if (!(bp->fw_cap & BNXT_FW_CAP_TRUSTED_VF))

		return !!(vf->flags & BNXT_VF_TRUST);



	bnxt_hwrm_func_qcfg_flags(bp, vf);

	return !!(vf->func_qcfg_flags & FUNC_QCFG_RESP_FLAGS_TRUSTED_VF);

}



static int bnxt_hwrm_set_trusted_vf(struct bnxt *bp, struct bnxt_vf_info *vf)

{

	struct hwrm_func_cfg_input req = {0};

	int rc;



	if (!(bp->fw_cap & BNXT_FW_CAP_TRUSTED_VF))

		return 0;



	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);

	req.fid = cpu_to_le16(vf->fw_fid);

	if (vf->flags & BNXT_VF_TRUST)

		req.flags = cpu_to_le32(FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE);

	else

		req.flags = cpu_to_le32(FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE);

	rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);

	if (rc)

		return -EIO;

	return 0;

}



int bnxt_set_vf_trust(struct net_device *dev, int vf_id, bool trusted)

{

	struct bnxt *bp = netdev_priv(dev);
@@ -135,6 +183,7 @@ int bnxt_set_vf_trust(struct net_device *dev, int vf_id, bool trusted) 
	else

		vf->flags &= ~BNXT_VF_TRUST;



	bnxt_hwrm_set_trusted_vf(bp, vf);

	return 0;

}
@@ -164,7 +213,7 @@ int bnxt_get_vf_config(struct net_device *dev, int vf_id, 
	else

		ivi->qos = 0;

	ivi->spoofchk = !!(vf->flags & BNXT_VF_SPOOFCHK);

	ivi->trusted = !!(vf->flags & BNXT_VF_TRUST);

	ivi->trusted = bnxt_is_trusted_vf(bp, vf);

	if (!(vf->flags & BNXT_VF_LINK_FORCED))

		ivi->linkstate = IFLA_VF_LINK_STATE_AUTO;

	else if (vf->flags & BNXT_VF_LINK_UP)
@@ -935,9 +984,10 @@ static int bnxt_vf_configure_mac(struct bnxt *bp, struct bnxt_vf_info *vf) 
	 * if the PF assigned MAC address is zero

	 */

	if (req->enables & cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR)) {

		bool trust = bnxt_is_trusted_vf(bp, vf);



		if (is_valid_ether_addr(req->dflt_mac_addr) &&

		    ((vf->flags & BNXT_VF_TRUST) ||

		     !is_valid_ether_addr(vf->mac_addr) ||

		    (trust || !is_valid_ether_addr(vf->mac_addr) ||

		     ether_addr_equal(req->dflt_mac_addr, vf->mac_addr))) {

			ether_addr_copy(vf->vf_mac_addr, req->dflt_mac_addr);

			return bnxt_hwrm_exec_fwd_resp(bp, vf, msg_size);
@@ -962,7 +1012,7 @@ static int bnxt_vf_validate_set_mac(struct bnxt *bp, struct bnxt_vf_info *vf) 
	 * Otherwise, it must match the VF MAC address if firmware spec >=

	 * 1.2.2

	 */

	if (vf->flags & BNXT_VF_TRUST) {

	if (bnxt_is_trusted_vf(bp, vf)) {

		mac_ok = true;

	} else if (is_valid_ether_addr(vf->mac_addr)) {

		if (ether_addr_equal((const u8 *)req->l2_addr, vf->mac_addr))

drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c

+1 −1
Original line number Diff line number Diff line
@@ -1290,7 +1290,7 @@ static int bnxt_tc_add_flow(struct bnxt *bp, u16 src_fid, 
		bnxt_tc_set_flow_dir(bp, flow, src_fid);



	if (!bnxt_tc_can_offload(bp, flow)) {

		rc = -ENOSPC;

		rc = -EOPNOTSUPP;

		goto free_node;

	}

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