Merge tag 'drm-next-2019-09-18' of git://anongit.freedesktop.org/drm/drm (574cc453) · Commits · 戴 / test

Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt

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		Amlogic specific extensions to the Synopsys Designware HDMI Controller
		======================================================================

		The Amlogic Meson Synopsys Designware Integration is composed of :
		- A Synopsys DesignWare HDMI Controller IP
		- A TOP control block controlling the Clocks and PHY
		- A custom HDMI PHY in order to convert video to TMDS signal
		___________________________________
		\| HDMI TOP \|<= HPD
		\|___________________________________\|
		\| \| \|
		\| Synopsys HDMI \| HDMI PHY \|=> TMDS
		\| Controller \|________________\|
		\|___________________________________\|<=> DDC

		The HDMI TOP block only supports HPD sensing.
		The Synopsys HDMI Controller interrupt is routed through the
		TOP Block interrupt.
		Communication to the TOP Block and the Synopsys HDMI Controller is done
		via a pair of dedicated addr+read/write registers.
		The HDMI PHY is configured by registers in the HHI register block.

		Pixel data arrives in 4:4:4 format from the VENC block and the VPU HDMI mux
		selects either the ENCI encoder for the 576i or 480i formats or the ENCP
		encoder for all the other formats including interlaced HD formats.

		The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate
		DVI timings for the HDMI controller.

		Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare
		HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF
		audio source interfaces.

		Required properties:
		- compatible: value should be different for each SoC family as :
		- GXBB (S905) : "amlogic,meson-gxbb-dw-hdmi"
		- GXL (S905X, S905D) : "amlogic,meson-gxl-dw-hdmi"
		- GXM (S912) : "amlogic,meson-gxm-dw-hdmi"
		followed by the common "amlogic,meson-gx-dw-hdmi"
		- G12A (S905X2, S905Y2, S905D2) : "amlogic,meson-g12a-dw-hdmi"
		- reg: Physical base address and length of the controller's registers.
		- interrupts: The HDMI interrupt number
		- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,
		and the Amlogic Meson venci clocks as described in
		Documentation/devicetree/bindings/clock/clock-bindings.txt,
		the clocks are soc specific, the clock-names should be "iahb", "isfr", "venci"
		- resets, resets-names: must have the phandles to the HDMI apb, glue and phy
		resets as described in :
		Documentation/devicetree/bindings/reset/reset.txt,
		the reset-names should be "hdmitx_apb", "hdmitx", "hdmitx_phy"

		Optional properties:
		- hdmi-supply: Optional phandle to an external 5V regulator to power the HDMI
		logic, as described in the file ../regulator/regulator.txt

		Required nodes:

		The connections to the HDMI ports are modeled using the OF graph
		bindings specified in Documentation/devicetree/bindings/graph.txt.

		The following table lists for each supported model the port number
		corresponding to each HDMI output and input.

		Port 0 Port 1
		-----------------------------------------
		S905 (GXBB) VENC Input TMDS Output
		S905X (GXL) VENC Input TMDS Output
		S905D (GXL) VENC Input TMDS Output
		S912 (GXM) VENC Input TMDS Output
		S905X2 (G12A) VENC Input TMDS Output
		S905Y2 (G12A) VENC Input TMDS Output
		S905D2 (G12A) VENC Input TMDS Output

		Example:

		hdmi-connector {
		compatible = "hdmi-connector";
		type = "a";

		port {
		hdmi_connector_in: endpoint {
		remote-endpoint = <&hdmi_tx_tmds_out>;
		};
		};
		};

		hdmi_tx: hdmi-tx@c883a000 {
		compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
		reg = <0x0 0xc883a000 0x0 0x1c>;
		interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
		resets = <&reset RESET_HDMITX_CAPB3>,
		<&reset RESET_HDMI_SYSTEM_RESET>,
		<&reset RESET_HDMI_TX>;
		reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
		clocks = <&clkc CLKID_HDMI_PCLK>,
		<&clkc CLKID_CLK81>,
		<&clkc CLKID_GCLK_VENCI_INT0>;
		clock-names = "isfr", "iahb", "venci";
		#address-cells = <1>;
		#size-cells = <0>;

		/* VPU VENC Input */
		hdmi_tx_venc_port: port@0 {
		reg = <0>;

		hdmi_tx_in: endpoint {
		remote-endpoint = <&hdmi_tx_out>;
		};
		};

		/* TMDS Output */
		hdmi_tx_tmds_port: port@1 {
		reg = <1>;

		hdmi_tx_tmds_out: endpoint {
		remote-endpoint = <&hdmi_connector_in>;
		};
		};
		};

Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml

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		# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
		# Copyright 2019 BayLibre, SAS
		%YAML 1.2
		---
		$id: "http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#"
		$schema: "http://devicetree.org/meta-schemas/core.yaml#"

		title: Amlogic specific extensions to the Synopsys Designware HDMI Controller

		maintainers:
		- Neil Armstrong <narmstrong@baylibre.com>

		description: \|
		The Amlogic Meson Synopsys Designware Integration is composed of
		- A Synopsys DesignWare HDMI Controller IP
		- A TOP control block controlling the Clocks and PHY
		- A custom HDMI PHY in order to convert video to TMDS signal
		___________________________________
		\| HDMI TOP \|<= HPD
		\|___________________________________\|
		\| \| \|
		\| Synopsys HDMI \| HDMI PHY \|=> TMDS
		\| Controller \|________________\|
		\|___________________________________\|<=> DDC

		The HDMI TOP block only supports HPD sensing.
		The Synopsys HDMI Controller interrupt is routed through the
		TOP Block interrupt.
		Communication to the TOP Block and the Synopsys HDMI Controller is done
		via a pair of dedicated addr+read/write registers.
		The HDMI PHY is configured by registers in the HHI register block.

		Pixel data arrives in "4:4:4" format from the VENC block and the VPU HDMI mux
		selects either the ENCI encoder for the 576i or 480i formats or the ENCP
		encoder for all the other formats including interlaced HD formats.

		The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate
		DVI timings for the HDMI controller.

		Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare
		HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF
		audio source interfaces.

		properties:
		compatible:
		oneOf:
		- items:
		- enum:
		- amlogic,meson-gxbb-dw-hdmi # GXBB (S905)
		- amlogic,meson-gxl-dw-hdmi # GXL (S905X, S905D)
		- amlogic,meson-gxm-dw-hdmi # GXM (S912)
		- const: amlogic,meson-gx-dw-hdmi
		- enum:
		- amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2)

		reg:
		maxItems: 1

		interrupts:
		maxItems: 1

		clocks:
		minItems: 3

		clock-names:
		items:
		- const: isfr
		- const: iahb
		- const: venci

		resets:
		minItems: 3

		reset-names:
		items:
		- const: hdmitx_apb
		- const: hdmitx
		- const: hdmitx_phy

		hdmi-supply:
		description: phandle to an external 5V regulator to power the HDMI logic
		allOf:
		- $ref: /schemas/types.yaml#/definitions/phandle

		port@0:
		type: object
		description:
		A port node pointing to the VENC Input port node.

		port@1:
		type: object
		description:
		A port node pointing to the TMDS Output port node.

		"#address-cells":
		const: 1

		"#size-cells":
		const: 0

		"#sound-dai-cells":
		const: 0

		required:
		- compatible
		- reg
		- interrupts
		- clocks
		- clock-names
		- resets
		- reset-names
		- port@0
		- port@1
		- "#address-cells"
		- "#size-cells"

		additionalProperties: false

		examples:
		- \|
		hdmi_tx: hdmi-tx@c883a000 {
		compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
		reg = <0xc883a000 0x1c>;
		interrupts = <57>;
		resets = <&reset_apb>, <&reset_hdmitx>, <&reset_hdmitx_phy>;
		reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
		clocks = <&clk_isfr>, <&clk_iahb>, <&clk_venci>;
		clock-names = "isfr", "iahb", "venci";
		#address-cells = <1>;
		#size-cells = <0>;

		/* VPU VENC Input */
		hdmi_tx_venc_port: port@0 {
		reg = <0>;

		hdmi_tx_in: endpoint {
		remote-endpoint = <&hdmi_tx_out>;
		};
		};

		/* TMDS Output */
		hdmi_tx_tmds_port: port@1 {
		reg = <1>;

		hdmi_tx_tmds_out: endpoint {
		remote-endpoint = <&hdmi_connector_in>;
		};
		};
		};

Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt

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		Amlogic Meson Display Controller
		================================

		The Amlogic Meson Display controller is composed of several components
		that are going to be documented below:

		DMC\|---------------VPU (Video Processing Unit)----------------\|------HHI------\|
		\| vd1 _______ _____________ _________________ \| \|
		D \|-------\| \|----\| \| \| \| \| HDMI PLL \|
		D \| vd2 \| VIU \| \| Video Post \| \| Video Encoders \|<---\|-----VCLK \|
		R \|-------\| \|----\| Processing \| \| \| \| \|
		\| osd2 \| \| \| \|---\| Enci ----------\|----\|-----VDAC------\|
		R \|-------\| CSC \|----\| Scalers \| \| Encp ----------\|----\|----HDMI-TX----\|
		A \| osd1 \| \| \| Blenders \| \| Encl ----------\|----\|---------------\|
		M \|-------\|______\|----\|____________\| \|________________\| \| \|
		___\|__________________________________________________________\|_______________\|


		VIU: Video Input Unit
		---------------------

		The Video Input Unit is in charge of the pixel scanout from the DDR memory.
		It fetches the frames addresses, stride and parameters from the "Canvas" memory.
		This part is also in charge of the CSC (Colorspace Conversion).
		It can handle 2 OSD Planes and 2 Video Planes.

		VPP: Video Post Processing
		--------------------------

		The Video Post Processing is in charge of the scaling and blending of the
		various planes into a single pixel stream.
		There is a special "pre-blending" used by the video planes with a dedicated
		scaler and a "post-blending" to merge with the OSD Planes.
		The OSD planes also have a dedicated scaler for one of the OSD.

		VENC: Video Encoders
		--------------------

		The VENC is composed of the multiple pixel encoders :
		- ENCI : Interlace Video encoder for CVBS and Interlace HDMI
		- ENCP : Progressive Video Encoder for HDMI
		- ENCL : LCD LVDS Encoder
		The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
		tree and provides the scanout clock to the VPP and VIU.
		The ENCI is connected to a single VDAC for Composite Output.
		The ENCI and ENCP are connected to an on-chip HDMI Transceiver.

		Device Tree Bindings:
		---------------------

		VPU: Video Processing Unit
		--------------------------

		Required properties:
		- compatible: value should be different for each SoC family as :
		- GXBB (S905) : "amlogic,meson-gxbb-vpu"
		- GXL (S905X, S905D) : "amlogic,meson-gxl-vpu"
		- GXM (S912) : "amlogic,meson-gxm-vpu"
		followed by the common "amlogic,meson-gx-vpu"
		- G12A (S905X2, S905Y2, S905D2) : "amlogic,meson-g12a-vpu"
		- reg: base address and size of he following memory-mapped regions :
		- vpu
		- hhi
		- reg-names: should contain the names of the previous memory regions
		- interrupts: should contain the VENC Vsync interrupt number
		- amlogic,canvas: phandle to canvas provider node as described in the file
		../soc/amlogic/amlogic,canvas.txt

		Optional properties:
		- power-domains: Optional phandle to associated power domain as described in
		the file ../power/power_domain.txt

		Required nodes:

		The connections to the VPU output video ports are modeled using the OF graph
		bindings specified in Documentation/devicetree/bindings/graph.txt.

		The following table lists for each supported model the port number
		corresponding to each VPU output.

		Port 0 Port 1
		-----------------------------------------
		S905 (GXBB) CVBS VDAC HDMI-TX
		S905X (GXL) CVBS VDAC HDMI-TX
		S905D (GXL) CVBS VDAC HDMI-TX
		S912 (GXM) CVBS VDAC HDMI-TX
		S905X2 (G12A) CVBS VDAC HDMI-TX
		S905Y2 (G12A) CVBS VDAC HDMI-TX
		S905D2 (G12A) CVBS VDAC HDMI-TX

		Example:

		tv-connector {
		compatible = "composite-video-connector";

		port {
		tv_connector_in: endpoint {
		remote-endpoint = <&cvbs_vdac_out>;
		};
		};
		};

		vpu: vpu@d0100000 {
		compatible = "amlogic,meson-gxbb-vpu";
		reg = <0x0 0xd0100000 0x0 0x100000>,
		<0x0 0xc883c000 0x0 0x1000>,
		<0x0 0xc8838000 0x0 0x1000>;
		reg-names = "vpu", "hhi", "dmc";
		interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
		#address-cells = <1>;
		#size-cells = <0>;

		/* CVBS VDAC output port */
		port@0 {
		reg = <0>;

		cvbs_vdac_out: endpoint {
		remote-endpoint = <&tv_connector_in>;
		};
		};
		};

Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml

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		# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
		# Copyright 2019 BayLibre, SAS
		%YAML 1.2
		---
		$id: "http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#"
		$schema: "http://devicetree.org/meta-schemas/core.yaml#"

		title: Amlogic Meson Display Controller

		maintainers:
		- Neil Armstrong <narmstrong@baylibre.com>

		description: \|
		The Amlogic Meson Display controller is composed of several components
		that are going to be documented below

		DMC\|---------------VPU (Video Processing Unit)----------------\|------HHI------\|
		\| vd1 _______ _____________ _________________ \| \|
		D \|-------\| \|----\| \| \| \| \| HDMI PLL \|
		D \| vd2 \| VIU \| \| Video Post \| \| Video Encoders \|<---\|-----VCLK \|
		R \|-------\| \|----\| Processing \| \| \| \| \|
		\| osd2 \| \| \| \|---\| Enci ----------\|----\|-----VDAC------\|
		R \|-------\| CSC \|----\| Scalers \| \| Encp ----------\|----\|----HDMI-TX----\|
		A \| osd1 \| \| \| Blenders \| \| Encl ----------\|----\|---------------\|
		M \|-------\|______\|----\|____________\| \|________________\| \| \|
		___\|__________________________________________________________\|_______________\|


		VIU: Video Input Unit
		---------------------

		The Video Input Unit is in charge of the pixel scanout from the DDR memory.
		It fetches the frames addresses, stride and parameters from the "Canvas" memory.
		This part is also in charge of the CSC (Colorspace Conversion).
		It can handle 2 OSD Planes and 2 Video Planes.

		VPP: Video Post Processing
		--------------------------

		The Video Post Processing is in charge of the scaling and blending of the
		various planes into a single pixel stream.
		There is a special "pre-blending" used by the video planes with a dedicated
		scaler and a "post-blending" to merge with the OSD Planes.
		The OSD planes also have a dedicated scaler for one of the OSD.

		VENC: Video Encoders
		--------------------

		The VENC is composed of the multiple pixel encoders
		- ENCI : Interlace Video encoder for CVBS and Interlace HDMI
		- ENCP : Progressive Video Encoder for HDMI
		- ENCL : LCD LVDS Encoder
		The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
		tree and provides the scanout clock to the VPP and VIU.
		The ENCI is connected to a single VDAC for Composite Output.
		The ENCI and ENCP are connected to an on-chip HDMI Transceiver.

		properties:
		compatible:
		oneOf:
		- items:
		- enum:
		- amlogic,meson-gxbb-vpu # GXBB (S905)
		- amlogic,meson-gxl-vpu # GXL (S905X, S905D)
		- amlogic,meson-gxm-vpu # GXM (S912)
		- const: amlogic,meson-gx-vpu
		- enum:
		- amlogic,meson-g12a-vpu # G12A (S905X2, S905Y2, S905D2)

		reg:
		maxItems: 2

		reg-names:
		items:
		- const: vpu
		- const: hhi

		interrupts:
		maxItems: 1

		power-domains:
		maxItems: 1
		description: phandle to the associated power domain

		port@0:
		type: object
		description:
		A port node pointing to the CVBS VDAC port node.

		port@1:
		type: object
		description:
		A port node pointing to the HDMI-TX port node.

		"#address-cells":
		const: 1

		"#size-cells":
		const: 0

		required:
		- compatible
		- reg
		- interrupts
		- port@0
		- port@1
		- "#address-cells"
		- "#size-cells"

		examples:
		- \|
		vpu: vpu@d0100000 {
		compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
		reg = <0xd0100000 0x100000>, <0xc883c000 0x1000>;
		reg-names = "vpu", "hhi";
		interrupts = <3>;
		#address-cells = <1>;
		#size-cells = <0>;

		/* CVBS VDAC output port */
		port@0 {
		reg = <0>;

		cvbs_vdac_out: endpoint {
		remote-endpoint = <&tv_connector_in>;
		};
		};

		/* HDMI TX output port */
		port@1 {
		reg = <1>;

		hdmi_tx_out: endpoint {
		remote-endpoint = <&hdmi_tx_in>;
		};
		};
		};

Documentation/devicetree/bindings/display/arm,pl11x.txt

+5 −4

Original line number	Diff line number	Diff line
		@@ -39,9 +39,11 @@ Required sub-nodes:

		- port: describes LCD panel signals, following the common binding
		for video transmitter interfaces; see
		Documentation/devicetree/bindings/media/video-interfaces.txt;
		when it is a TFT panel, the port's endpoint must define the
		following property:
		Documentation/devicetree/bindings/media/video-interfaces.txt

		Deprecated properties:
		The port's endbpoint subnode had this, now deprecated property
		in the past. Drivers should be able to survive without it:

		- arm,pl11x,tft-r0g0b0-pads: an array of three 32-bit values,
		defining the way CLD pads are wired up; first value
		@@ -80,7 +82,6 @@ Example:
		port {
		clcd_pads: endpoint {
		remote-endpoint = <&clcd_panel>;
		arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
		};
		};

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