Commit 57253ccd authored by Hyunki Koo's avatar Hyunki Koo Committed by Greg Kroah-Hartman
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serial: samsung: 32-bit access for TX/RX hold registers



Support 32-bit access for the TX/RX hold registers UTXH and URXH.

This is required for some newer SoCs.

Signed-off-by: default avatarHyunki Koo <hyunki00.koo@samsung.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Tested on Odroid HC1 (Exynos5422):
Tested-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200506080242.18623-3-hyunki00.koo@samsung.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 7ad3bee4
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+57 −5
Original line number Diff line number Diff line
@@ -154,10 +154,33 @@ struct s3c24xx_uart_port {
#define portaddrl(port, reg) \
	((unsigned long *)(unsigned long)((port)->membase + (reg)))

#define rd_reg(port, reg) (readb_relaxed(portaddr(port, reg)))
static u32 rd_reg(struct uart_port *port, u32 reg)
{
	switch (port->iotype) {
	case UPIO_MEM:
		return readb_relaxed(portaddr(port, reg));
	case UPIO_MEM32:
		return readl_relaxed(portaddr(port, reg));
	default:
		return 0;
	}
	return 0;
}

#define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))

#define wr_reg(port, reg, val) writeb_relaxed(val, portaddr(port, reg))
static void wr_reg(struct uart_port *port, u32 reg, u32 val)
{
	switch (port->iotype) {
	case UPIO_MEM:
		writeb_relaxed(val, portaddr(port, reg));
		break;
	case UPIO_MEM32:
		writel_relaxed(val, portaddr(port, reg));
		break;
	}
}

#define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))

/* Byte-order aware bit setting/clearing functions. */
@@ -1974,7 +1997,7 @@ static int s3c24xx_serial_probe(struct platform_device *pdev)
	struct device_node *np = pdev->dev.of_node;
	struct s3c24xx_uart_port *ourport;
	int index = probe_index;
	int ret;
	int ret, prop = 0;

	if (np) {
		ret = of_alias_get_id(np, "serial");
@@ -2000,10 +2023,27 @@ static int s3c24xx_serial_probe(struct platform_device *pdev)
			dev_get_platdata(&pdev->dev) :
			ourport->drv_data->def_cfg;

	if (np)
	if (np) {
		of_property_read_u32(np,
			"samsung,uart-fifosize", &ourport->port.fifosize);

		if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
			switch (prop) {
			case 1:
				ourport->port.iotype = UPIO_MEM;
				break;
			case 4:
				ourport->port.iotype = UPIO_MEM32;
				break;
			default:
				dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
						prop);
				ret = -EINVAL;
				break;
			}
		}
	}

	if (ourport->drv_data->fifosize[index])
		ourport->port.fifosize = ourport->drv_data->fifosize[index];
	else if (ourport->info->fifosize)
@@ -2587,6 +2627,18 @@ module_platform_driver(samsung_serial_driver);
 * Early console.
 */

static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val)
{
	switch (port->iotype) {
	case UPIO_MEM:
		writeb(val, portaddr(port, reg));
		break;
	case UPIO_MEM32:
		writel(val, portaddr(port, reg));
		break;
	}
}

struct samsung_early_console_data {
	u32 txfull_mask;
};
@@ -2612,7 +2664,7 @@ static void samsung_early_putc(struct uart_port *port, int c)
	else
		samsung_early_busyuart(port);

	writeb(c, port->membase + S3C2410_UTXH);
	wr_reg_barrier(port, S3C2410_UTXH, c);
}

static void samsung_early_write(struct console *con, const char *s,