Commit 570a3743 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2018-11-30' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "This weeks instalment of fixes. Looks fairly like business as usual
  and everything seems to rolling along. There was one MST fix applied
  and reverted in the misc tree, but otherwise nothing too strange in
  here.

  core:
   - incorrect master setting on error fix

  i915:
   - only GVT fixes this week:
      * one MOCS register load
      * rpm lock fix
      * use after free

  rcar-du:
   - regression fix for group start

  amdgpu:
   - DP MST fix
   - GPUVM fix for huge pages
   - RLC fix for vega20

  ast:
   - fix EDID reading stability
   - ioreg free fix

  meson:
   - sleep in irq fix
   - vblank fixes
   - array boundary fix"

* tag 'drm-fixes-2018-11-30' of git://anongit.freedesktop.org/drm/drm:
  drm/ast: fixed reading monitor EDID not stable issue
  drm/ast: Fix incorrect free on ioregs
  Revert "drm/dp_mst: Skip validating ports during destruction, just ref"
  drm/amdgpu: Add delay after enable RLC ucode
  drm/amdgpu: Avoid endless loop in GPUVM fragment processing
  drm/amdgpu: Cast to uint64_t before left shift
  drm/meson: add support for 1080p25 mode
  drm/meson: Fix OOB memory accesses in meson_viu_set_osd_lut()
  drm/meson: Enable fast_io in meson_dw_hdmi_regmap_config
  drm/meson: Fixes for drm_crtc_vblank_on/off support
  drm: set is_master to 0 upon drm_new_set_master() failure
  drm/dp_mst: Skip validating ports during destruction, just ref
  drm: rcar-du: Fix DU3 start/stop on M3-N
  drm/amd/dm: Understand why attaching path/tile properties are needed
  drm/amd/dm: Don't forget to attach MST encoders
  drm/i915/gvt: Avoid use-after-free iterating the gtt list
  drm/i915/gvt: ensure gpu is powered before do i915_gem_gtt_insert
  drm/i915/gvt: not to touch undefined MOCS registers
parents e9eaf72e ebcdcef3

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+8 −6
Original line number Diff line number Diff line
@@ -181,7 +181,7 @@ static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, 


	if (level == adev->vm_manager.root_level)

		/* For the root directory */

		return round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift;

		return round_up(adev->vm_manager.max_pfn, 1ULL << shift) >> shift;

	else if (level != AMDGPU_VM_PTB)

		/* Everything in between */

		return 512;
@@ -1656,9 +1656,11 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, 
			if (!amdgpu_vm_pt_descendant(adev, &cursor))

				return -ENOENT;

			continue;

		} else if (frag >= parent_shift) {

		} else if (frag >= parent_shift &&

			   cursor.level - 1 != adev->vm_manager.root_level) {

			/* If the fragment size is even larger than the parent

			 * shift we should go up one level and check it again.

			 * shift we should go up one level and check it again

			 * unless one level up is the root level.

			 */

			if (!amdgpu_vm_pt_ancestor(&cursor))

				return -ENOENT;
@@ -1666,10 +1668,10 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, 
		}



		/* Looks good so far, calculate parameters for the update */

		incr = AMDGPU_GPU_PAGE_SIZE << shift;

		incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;

		mask = amdgpu_vm_entries_mask(adev, cursor.level);

		pe_start = ((cursor.pfn >> shift) & mask) * 8;

		entry_end = (mask + 1) << shift;

		entry_end = (uint64_t)(mask + 1) << shift;

		entry_end += cursor.pfn & ~(entry_end - 1);

		entry_end = min(entry_end, end);
@@ -1682,7 +1684,7 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, 
					      flags | AMDGPU_PTE_FRAG(frag));



			pe_start += nptes * 8;

			dst += nptes * AMDGPU_GPU_PAGE_SIZE << shift;

			dst += (uint64_t)nptes * AMDGPU_GPU_PAGE_SIZE << shift;



			frag_start = upd_end;

			if (frag_start >= frag_end) {

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+4 −3
Original line number Diff line number Diff line
@@ -2440,12 +2440,13 @@ static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) 
#endif



	WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);

	udelay(50);



	/* carrizo do enable cp interrupt after cp inited */

	if (!(adev->flags & AMD_IS_APU))

	if (!(adev->flags & AMD_IS_APU)) {

		gfx_v9_0_enable_gui_idle_interrupt(adev, true);



		udelay(50);

	}



#ifdef AMDGPU_RLC_DEBUG_RETRY

	/* RLC_GPM_GENERAL_6 : RLC Ucode version */

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

+2 −3
Original line number Diff line number Diff line
@@ -342,10 +342,9 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, 
		master->connector_id);



	aconnector->mst_encoder = dm_dp_create_fake_mst_encoder(master);

	drm_connector_attach_encoder(&aconnector->base,

				     &aconnector->mst_encoder->base);



	/*

	 * TODO: understand why this one is needed

	 */

	drm_object_attach_property(

		&connector->base,

		dev->mode_config.path_property,

drivers/gpu/drm/ast/ast_main.c

+2 −1
Original line number Diff line number Diff line
@@ -583,6 +583,7 @@ void ast_driver_unload(struct drm_device *dev) 
	drm_mode_config_cleanup(dev);



	ast_mm_fini(ast);

	if (ast->ioregs != ast->regs + AST_IO_MM_OFFSET)

		pci_iounmap(dev->pdev, ast->ioregs);

	pci_iounmap(dev->pdev, ast->regs);

	kfree(ast);

drivers/gpu/drm/ast/ast_mode.c

+30 −6
Original line number Diff line number Diff line
@@ -973,9 +973,21 @@ static int get_clock(void *i2c_priv) 
{

	struct ast_i2c_chan *i2c = i2c_priv;

	struct ast_private *ast = i2c->dev->dev_private;

	uint32_t val;

	uint32_t val, val2, count, pass;



	count = 0;

	pass = 0;

	val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;

	do {

		val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;

		if (val == val2) {

			pass++;

		} else {

			pass = 0;

			val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;

		}

	} while ((pass < 5) && (count++ < 0x10000));



	val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4;

	return val & 1 ? 1 : 0;

}
@@ -983,9 +995,21 @@ static int get_data(void *i2c_priv) 
{

	struct ast_i2c_chan *i2c = i2c_priv;

	struct ast_private *ast = i2c->dev->dev_private;

	uint32_t val;

	uint32_t val, val2, count, pass;



	count = 0;

	pass = 0;

	val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;

	do {

		val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;

		if (val == val2) {

			pass++;

		} else {

			pass = 0;

			val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;

		}

	} while ((pass < 5) && (count++ < 0x10000));



	val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5;

	return val & 1 ? 1 : 0;

}
@@ -998,7 +1022,7 @@ static void set_clock(void *i2c_priv, int clock) 


	for (i = 0; i < 0x10000; i++) {

		ujcrb7 = ((clock & 0x01) ? 0 : 1);

		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfe, ujcrb7);

		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7);

		jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01);

		if (ujcrb7 == jtemp)

			break;
@@ -1014,7 +1038,7 @@ static void set_data(void *i2c_priv, int data) 


	for (i = 0; i < 0x10000; i++) {

		ujcrb7 = ((data & 0x01) ? 0 : 1) << 2;

		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfb, ujcrb7);

		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7);

		jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04);

		if (ujcrb7 == jtemp)

			break;

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