net: hns3: remove a redundant register macro definition (5705b451) · Commits · 戴 / test

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

+0 −1

Original line number	Diff line number	Diff line
		@@ -16,7 +16,6 @@
		#define HCLGE_RAS_REG_NFE_MASK 0xFF00
		#define HCLGE_RAS_REG_ROCEE_ERR_MASK 0x3000000

		#define HCLGE_VECTOR0_PF_OTHER_INT_STS_REG 0x20800
		#define HCLGE_VECTOR0_REG_MSIX_MASK 0x1FF00

		#define HCLGE_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

+5 −7

Original line number	Diff line number	Diff line
		@@ -2968,13 +2968,11 @@ static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf,

		static u32 hclge_check_event_cause(struct hclge_dev hdev, u32 clearval)
		{
		u32 rst_src_reg, cmdq_src_reg, msix_src_reg;
		u32 cmdq_src_reg, msix_src_reg;

		/* fetch the events from their corresponding regs */
		rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
		cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
		msix_src_reg = hclge_read_dev(&hdev->hw,
		HCLGE_VECTOR0_PF_OTHER_INT_STS_REG);
		msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);

		/* Assumption: If by any chance reset and mailbox events are reported
		* together then we will only process reset event in this go and will
		@@ -2984,7 +2982,7 @@ static u32 hclge_check_event_cause(struct hclge_dev hdev, u32 clearval)
		*
		* check for vector0 reset event sources
		*/
		if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
		if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) {
		dev_info(&hdev->pdev->dev, "IMP reset interrupt\n");
		set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
		set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
		@@ -2993,7 +2991,7 @@ static u32 hclge_check_event_cause(struct hclge_dev hdev, u32 clearval)
		return HCLGE_VECTOR0_EVENT_RST;
		}

		if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
		if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) {
		dev_info(&hdev->pdev->dev, "global reset interrupt\n");
		set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
		set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
		@@ -3483,7 +3481,7 @@ static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev,
		/* first, resolve any unknown reset type to the known type(s) */
		if (test_bit(HNAE3_UNKNOWN_RESET, addr)) {
		u32 msix_sts_reg = hclge_read_dev(&hdev->hw,
		HCLGE_VECTOR0_PF_OTHER_INT_STS_REG);
		HCLGE_MISC_VECTOR_INT_STS);
		/* we will intentionally ignore any errors from this function
		* as we will end up in some reset request in any case
		*/

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