Merge branches 'arm/renesas', 'arm/qcom', 'arm/mediatek', 'arm/omap',... (56fbacc9) · Commits · 戴 / test

Documentation/arm64/silicon-errata.rst

+3 −0

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		@@ -125,6 +125,9 @@ stable kernels.
		\| Cavium \| ThunderX2 Core \| #219 \| CAVIUM_TX2_ERRATUM_219 \|
		+----------------+-----------------+-----------------+-----------------------------+
		+----------------+-----------------+-----------------+-----------------------------+
		\| Marvell \| ARM-MMU-500 \| #582743 \| N/A \|
		+----------------+-----------------+-----------------+-----------------------------+
		+----------------+-----------------+-----------------+-----------------------------+
		\| Freescale/NXP \| LS2080A/LS1043A \| A-008585 \| FSL_ERRATUM_A008585 \|
		+----------------+-----------------+-----------------+-----------------------------+
		+----------------+-----------------+-----------------+-----------------------------+

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		@@ -37,7 +37,18 @@ properties:
		- enum:
		- qcom,sc7180-smmu-500
		- qcom,sdm845-smmu-500
		- qcom,sm8150-smmu-500
		- qcom,sm8250-smmu-500
		- const: arm,mmu-500
		- description: Marvell SoCs implementing "arm,mmu-500"
		items:
		- const: marvell,ap806-smmu-500
		- const: arm,mmu-500
		- description: NVIDIA SoCs that program two ARM MMU-500s identically
		items:
		- enum:
		- nvidia,tegra194-smmu
		- const: nvidia,smmu-500
		- items:
		- const: arm,mmu-500
		- const: arm,smmu-v2
		@@ -55,7 +66,8 @@ properties:
		- cavium,smmu-v2

		reg:
		maxItems: 1
		minItems: 1
		maxItems: 2

		'#global-interrupts':
		description: The number of global interrupts exposed by the device.
		@@ -138,6 +150,23 @@ required:

		additionalProperties: false

		allOf:
		- if:
		properties:
		compatible:
		contains:
		enum:
		- nvidia,tegra194-smmu
		then:
		properties:
		reg:
		minItems: 2
		maxItems: 2
		else:
		properties:
		reg:
		maxItems: 1

		examples:
		- \|+
		/* SMMU with stream matching or stream indexing */

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		@@ -58,6 +58,7 @@ Required properties:
		- compatible : must be one of the following string:
		"mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
		"mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
		"mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW.
		"mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses
		generation one m4u HW.
		"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
		@@ -78,6 +79,7 @@ Required properties:
		Specifies the mtk_m4u_id as defined in
		dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623
		dt-binding/memory/mt2712-larb-port.h for mt2712,
		dt-binding/memory/mt6779-larb-port.h for mt6779,
		dt-binding/memory/mt8173-larb-port.h for mt8173, and
		dt-binding/memory/mt8183-larb-port.h for mt8183.

+1 −0

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		@@ -5,7 +5,7 @@ The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
		Mediatek SMI have two generations of HW architecture, here is the list
		which generation the SoCs use:
		generation 1: mt2701 and mt7623.
		generation 2: mt2712, mt8173 and mt8183.
		generation 2: mt2712, mt6779, mt8173 and mt8183.

		There's slight differences between the two SMI, for generation 2, the
		register which control the iommu port is at each larb's register base. But
		@@ -18,6 +18,7 @@ Required properties:
		- compatible : must be one of :
		"mediatek,mt2701-smi-common"
		"mediatek,mt2712-smi-common"
		"mediatek,mt6779-smi-common"
		"mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
		"mediatek,mt8173-smi-common"
		"mediatek,mt8183-smi-common"
		@@ -35,7 +36,7 @@ Required properties:
		and these 2 option clocks for generation 2 smi HW:
		- "gals0": the path0 clock of GALS(Global Async Local Sync).
		- "gals1": the path1 clock of GALS(Global Async Local Sync).
		Here is the list which has this GALS: mt8183.
		Here is the list which has this GALS: mt6779 and mt8183.

		Example:
		smi_common: smi@14022000 {