Commit 56f48c1d authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Unify the low level dbuf code 



The low level dbuf slice code is rather inconsitent with its
functiona naming and organization. Make it more consistent.

Also share the enable/disable functions between all platforms
since the same code works just fine for all of them.

Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200225171125.28885-8-ville.syrjala@linux.intel.com


Reviewed-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
parent b3f1ff5b

drivers/gpu/drm/i915/display/intel_display.c

+2 −4
Original line number Diff line number Diff line
@@ -15213,9 +15213,8 @@ static void icl_dbuf_slice_pre_update(struct intel_atomic_state *state) 
	u8 required_slices = state->enabled_dbuf_slices_mask;

	u8 slices_union = hw_enabled_slices | required_slices;













	/* If 2nd DBuf slice required, enable it here */















	if (INTEL_GEN(dev_priv) >= 11 && slices_union != hw_enabled_slices)













		icl_dbuf_slices_update(dev_priv, slices_union);













		gen9_dbuf_slices_update(dev_priv, slices_union);















}





























static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)









@@ -15224,9 +15223,8 @@ static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)













	u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_mask;















	u8 required_slices = state->enabled_dbuf_slices_mask;



























	/* If 2nd DBuf slice is no more required disable it */















	if (INTEL_GEN(dev_priv) >= 11 && required_slices != hw_enabled_slices)













		icl_dbuf_slices_update(dev_priv, required_slices);













		gen9_dbuf_slices_update(dev_priv, required_slices);















}





























static void skl_commit_modeset_enables(struct intel_atomic_state *state)

































drivers/gpu/drm/i915/display/intel_display_power.c



+19
−25






























Original line number
Diff line number
Diff line








@@ -4491,7 +4491,7 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)













	mutex_unlock(&power_domains->lock);















}





























static void intel_dbuf_slice_set(struct drm_i915_private *dev_priv,













static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,















				enum dbuf_slice slice, bool enable)















{















	i915_reg_t reg = DBUF_CTL_S(slice);









@@ -4499,7 +4499,10 @@ static void intel_dbuf_slice_set(struct drm_i915_private *dev_priv,













	u32 val;































	val = intel_de_read(dev_priv, reg);













	val = enable ? (val | DBUF_POWER_REQUEST) : (val & ~DBUF_POWER_REQUEST);













	if (enable)













		val |= DBUF_POWER_REQUEST;













	else













		val &= ~DBUF_POWER_REQUEST;















	intel_de_write(dev_priv, reg, val);















	intel_de_posting_read(dev_priv, reg);















	udelay(10);









@@ -4510,17 +4513,7 @@ static void intel_dbuf_slice_set(struct drm_i915_private *dev_priv,













		 slice, enable ? "enable" : "disable");















}





























static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)













{













	icl_dbuf_slices_update(dev_priv, BIT(DBUF_S1));













}



























static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)













{













	icl_dbuf_slices_update(dev_priv, 0);













}



























void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,













void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,















			     u8 req_slices)















{















	int num_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;









@@ -4544,28 +4537,29 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,













	mutex_lock(&power_domains->lock);































	for (slice = DBUF_S1; slice < num_slices; slice++)













		intel_dbuf_slice_set(dev_priv, slice,













				     req_slices & BIT(slice));













		gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice));































	dev_priv->enabled_dbuf_slices_mask = req_slices;































	mutex_unlock(&power_domains->lock);















}





























static void icl_dbuf_enable(struct drm_i915_private *dev_priv)













static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)















{













	skl_ddb_get_hw_state(dev_priv);













	dev_priv->enabled_dbuf_slices_mask =













		intel_enabled_dbuf_slices_mask(dev_priv);





























	/*















	 * Just power up at least 1 slice, we will















	 * figure out later which slices we have and what we need.















	 */













	icl_dbuf_slices_update(dev_priv, dev_priv->enabled_dbuf_slices_mask |













			       BIT(DBUF_S1));













	gen9_dbuf_slices_update(dev_priv, BIT(DBUF_S1) |













				dev_priv->enabled_dbuf_slices_mask);















}





























static void icl_dbuf_disable(struct drm_i915_private *dev_priv)













static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)















{













	icl_dbuf_slices_update(dev_priv, 0);













	gen9_dbuf_slices_update(dev_priv, 0);















}































static void icl_mbus_init(struct drm_i915_private *dev_priv)










@@ -5125,7 +5119,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,













	intel_cdclk_init_hw(dev_priv);































	/* 5. Enable DBUF. */













	icl_dbuf_enable(dev_priv);













	gen9_dbuf_enable(dev_priv);































	/* 6. Setup MBUS. */















	icl_mbus_init(dev_priv);









@@ -5148,7 +5142,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)













	/* 1. Disable all display engine functions -> aready done */































	/* 2. Disable DBUF */













	icl_dbuf_disable(dev_priv);













	gen9_dbuf_disable(dev_priv);































	/* 3. Disable CD clock */















	intel_cdclk_uninit_hw(dev_priv);

































drivers/gpu/drm/i915/display/intel_display_power.h



+3
−3






























Original line number
Diff line number
Diff line








@@ -316,13 +316,13 @@ enum dbuf_slice {













	DBUF_S2,















};





























void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,













			     u8 req_slices);





























#define with_intel_display_power(i915, domain, wf) \















	for ((wf) = intel_display_power_get((i915), (domain)); (wf); \















	     intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)





























void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,













			    u8 req_slices);





























void chv_phy_powergate_lanes(struct intel_encoder *encoder,















			     bool override, unsigned int mask);















bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,



































































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