Commit 56e9461a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'openrisc-for-linus' of git://github.com/openrisc/linux 

Pull Openrisc updates from Stafford Horne:

 - changes to MAINTAINER for openrisc

 - probably biggest actual change is the move to memblock from bootmem

 - ... plus several bug and build fixes

* tag 'openrisc-for-linus' of git://github.com/openrisc/linux:
  openrisc: prevent VGA console, fix builds
  openrisc: include l.swa in check for write data pagefault
  openrisc: Updates after openrisc.net has been lost
  openrisc: Consolidate setup to use memblock instead of bootmem
  openrisc: remove the redundant of_platform_populate
  openrisc: add NR_CPUS Kconfig default value
  openrisc: Support both old (or32) and new (or1k) toolchain
  openrisc: Add thread-local storage (TLS) support
  openrisc: restore all regs on rt_sigreturn
  openrisc: fix PTRS_PER_PGD define
parents 709c12e3 7c7808ce

MAINTAINERS

+4 −2
Original line number Diff line number Diff line
@@ -8977,9 +8977,11 @@ F: drivers/of/resolver.c 


OPENRISC ARCHITECTURE

M:	Jonas Bonn <jonas@southpole.se>

W:	http://openrisc.net

M:	Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>

M:	Stafford Horne <shorne@gmail.com>

L:	openrisc@lists.librecores.org

W:	http://openrisc.io

S:	Maintained

T:	git git://openrisc.net/~jonas/linux

F:	arch/openrisc/



OPENVSWITCH

arch/openrisc/Kconfig

+4 −0
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@@ -26,6 +26,7 @@ config OPENRISC 
	select HAVE_DEBUG_STACKOVERFLOW

	select OR1K_PIC

	select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1

	select NO_BOOTMEM



config MMU

	def_bool y
@@ -98,6 +99,9 @@ config OPENRISC_HAVE_INST_DIV 
	  Select this if your implementation has a hardware divide instruction

endmenu



config NR_CPUS

	int

	default "1"



source kernel/Kconfig.hz

source kernel/Kconfig.preempt

arch/openrisc/README.openrisc

+4 −4
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@@ -6,7 +6,7 @@ target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k). 


For information about OpenRISC processors and ongoing development:



	website		http://openrisc.net

	website		http://openrisc.io



For more information about Linux on OpenRISC, please contact South Pole AB.
@@ -24,17 +24,17 @@ In order to build and run Linux for OpenRISC, you'll need at least a basic 
toolchain and, perhaps, the architectural simulator.  Steps to get these bits

in place are outlined here.



1)  The toolchain can be obtained from openrisc.net.  Instructions for building

1)  The toolchain can be obtained from openrisc.io.  Instructions for building

a toolchain can be found at:



http://openrisc.net/toolchain-build.html

https://github.com/openrisc/tutorials



2) or1ksim (optional)



or1ksim is the architectural simulator which will allow you to actually run

your OpenRISC Linux kernel if you don't have an OpenRISC processor at hand.



	git clone git://openrisc.net/jonas/or1ksim-svn

	git clone https://github.com/openrisc/or1ksim.git



	cd or1ksim

	./configure --prefix=$OPENRISC_PREFIX

arch/openrisc/TODO.openrisc

+0 −3
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@@ -5,9 +5,6 @@ that are due for investigation shortly, i.e. our TODO list: 


-- Implement the rest of the DMA API... dma_map_sg, etc.



-- Consolidate usage of memblock and bootmem... move everything over to

   memblock.



-- Finish the renaming cleanup... there are references to or32 in the code

   which was an older name for the architecture.  The name we've settled on is

   or1k and this change is slowly trickling through the stack.  For the time

arch/openrisc/include/asm/pgalloc.h

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@@ -23,7 +23,6 @@ 
#include <linux/threads.h>

#include <linux/mm.h>

#include <linux/memblock.h>

#include <linux/bootmem.h>



extern int mem_init_done;

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