Commit 56d8adc5 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt
Browse files

Merge remote branch 'jwb/next' into next

parents f4b98415 ee2ffd8b
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+52 −0
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PPC4xx Clock Power Management (CPM) node

Required properties:
	- compatible		: compatible list, currently only "ibm,cpm"
	- dcr-access-method	: "native"
	- dcr-reg		: < DCR register range >

Optional properties:
	- er-offset		: All 4xx SoCs with a CPM controller have
				  one of two different order for the CPM
				  registers. Some have the CPM registers
				  in the following order (ER,FR,SR). The
				  others have them in the following order
				  (SR,ER,FR). For the second case set
				  er-offset = <1>.
	- unused-units		: specifier consist of one cell. For each
				  bit in the cell, the corresponding bit
				  in CPM will be set to turn off unused
				  devices.
	- idle-doze		: specifier consist of one cell. For each
				  bit in the cell, the corresponding bit
				  in CPM will be set to turn off unused
				  devices. This is usually just CPM[CPU].
	- standby		: specifier consist of one cell. For each
				  bit in the cell, the corresponding bit
				  in CPM will be set on standby and
				  restored on resume.
	- suspend		: specifier consist of one cell. For each
				  bit in the cell, the corresponding bit
				  in CPM will be set on suspend (mem) and
				  restored on resume. Note, for standby
				  and suspend the corresponding bits can
				  be different or the same. Usually for
				  standby only class 2 and 3 units are set.
				  However, the interface does not care.
				  If they are the same, the additional
				  power saving will be seeing if support
				  is available to put the DDR in self
				  refresh mode and any additional power
				  saving techniques for the specific SoC.

Example:
	CPM0: cpm {
		compatible = "ibm,cpm";
		dcr-access-method = "native";
		dcr-reg = <0x160 0x003>;
		er-offset = <0>;
		unused-units = <0x00000100>;
		idle-doze = <0x02000000>;
		standby = <0xfeff0000>;
		suspend = <0xfeff791d>;
};
+10 −3
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@@ -212,7 +212,7 @@ config ARCH_HIBERNATION_POSSIBLE
config ARCH_SUSPEND_POSSIBLE
	def_bool y
	depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \
		   PPC_85xx || PPC_86xx || PPC_PSERIES
		   PPC_85xx || PPC_86xx || PPC_PSERIES || 44x || 40x

config PPC_DCR_NATIVE
	bool
@@ -598,13 +598,11 @@ config EXTRA_TARGETS

	  If unsure, leave blank

if !44x || BROKEN
config ARCH_WANTS_FREEZER_CONTROL
	def_bool y
	depends on ADB_PMU

source kernel/power/Kconfig
endif

config SECCOMP
	bool "Enable seccomp to safely compute untrusted bytecode"
@@ -685,6 +683,15 @@ config FSL_PMC
	  Freescale MPC85xx/MPC86xx power management controller support
	  (suspend/resume). For MPC83xx see platforms/83xx/suspend.c

config PPC4xx_CPM
	bool
	default y
	depends on SUSPEND && (44x || 40x)
	help
	  PPC4xx Clock Power Management (CPM) support (suspend/resume).
	  It also enables support for two different idle states (idle-wait
	  and idle-doze).

config 4xx_SOC
	bool

+9 −22
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@@ -105,6 +105,15 @@
		dcr-reg = <0x00c 0x002>;
	};

	CPM0: cpm {
		compatible = "ibm,cpm";
		dcr-access-method = "native";
		dcr-reg = <0x160 0x003>;
		unused-units = <0x00000100>;
		idle-doze = <0x02000000>;
		standby = <0xfeff791d>;
	};

	L2C0: l2c {
		compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
		dcr-reg = <0x020 0x008		/* Internal SRAM DCR's */
@@ -270,28 +279,6 @@
				interrupts = <0x1 0x4>;
			};

			UART2: serial@ef600500 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0xef600500 0x00000008>;
				virtual-reg = <0xef600500>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				current-speed = <0>; /* Filled in by U-Boot */
				interrupt-parent = <&UIC1>;
				interrupts = <28 0x4>;
			};

			UART3: serial@ef600600 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0xef600600 0x00000008>;
				virtual-reg = <0xef600600>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				current-speed = <0>; /* Filled in by U-Boot */
				interrupt-parent = <&UIC1>;
				interrupts = <29 0x4>;
			};

			IIC0: i2c@ef600700 {
				compatible = "ibm,iic-460ex", "ibm,iic";
				reg = <0xef600700 0x00000014>;
+9 −0
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@@ -82,6 +82,15 @@
		interrupt-parent = <&UIC0>;
	};

	CPM0: cpm {
		compatible = "ibm,cpm";
		dcr-access-method = "native";
		dcr-reg = <0x0b0 0x003>;
		unused-units = <0x00000000>;
		idle-doze = <0x02000000>;
		standby = <0xe3e74800>;
	};

	plb {
		compatible = "ibm,plb-405ex", "ibm,plb4";
		#address-cells = <1>;
+5 −0
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@@ -12,6 +12,8 @@ CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_KILAUEA=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
# CONFIG_WALNUT is not set
CONFIG_SPARSE_IRQ=y
CONFIG_PCI=y
@@ -42,6 +44,9 @@ CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_NDFC=y
CONFIG_PROC_DEVICETREE=y
CONFIG_PM=y
CONFIG_SUSPEND=y
CONFIG_PPC4xx_CPM=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
# CONFIG_MISC_DEVICES is not set
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