Commit 56ae5833 authored by Yoichi Yuasa's avatar Yoichi Yuasa Committed by Ralf Baechle
Browse files

[MIPS] Rewrite GALILEO_INL/GALILEO_OUTL to GT_READ/GT_WRITE 



This patch has rewritten GALILEO_INL/GALILEO_OUTL using GT_READ/GT_WRITE.
This patch tested on Cobalt Qube2.

Signed-off-by: default avatarYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 4e3884fc

arch/mips/cobalt/irq.c

+14 −17
Original line number Diff line number Diff line
@@ -45,25 +45,22 @@ static inline void galileo_irq(void) 
{

	unsigned int mask, pending, devfn;



	mask = GALILEO_INL(GT_INTRMASK_OFS);

	pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask;

	mask = GT_READ(GT_INTRMASK_OFS);

	pending = GT_READ(GT_INTRCAUSE_OFS) & mask;



	if (pending & GALILEO_INTR_T0EXP) {



		GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS);

	if (pending & GT_INTR_T0EXP_MSK) {

		GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK);

		do_IRQ(COBALT_GALILEO_IRQ);



	} else if (pending & GALILEO_INTR_RETRY_CTR) {



		devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8;

		GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS);

		printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n",

	} else if (pending & GT_INTR_RETRYCTR0_MSK) {

		devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8;

		GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK);

		printk(KERN_WARNING

		       "Galileo: PCI retry count exceeded (%02x.%u)\n",

		       PCI_SLOT(devfn), PCI_FUNC(devfn));



	} else {



		GALILEO_OUTL(mask & ~pending, GT_INTRMASK_OFS);

		printk(KERN_WARNING "Galileo: masking unexpected interrupt %08x\n", pending);

		GT_WRITE(GT_INTRMASK_OFS, mask & ~pending);

		printk(KERN_WARNING

		       "Galileo: masking unexpected interrupt %08x\n", pending);

	}

}
@@ -104,7 +101,7 @@ void __init arch_init_irq(void) 
	 * Mask all Galileo interrupts. The Galileo

	 * handler is set in cobalt_timer_setup()

	 */

	GALILEO_OUTL(0, GT_INTRMASK_OFS);

	GT_WRITE(GT_INTRMASK_OFS, 0);



	init_i8259_irqs();				/*  0 ... 15 */

	mips_cpu_irq_init(COBALT_CPU_IRQ);		/* 16 ... 23 */

arch/mips/cobalt/setup.c

+8 −8
Original line number Diff line number Diff line
@@ -51,23 +51,23 @@ const char *get_system_type(void) 
void __init plat_timer_setup(struct irqaction *irq)

{

	/* Load timer value for HZ (TCLK is 50MHz) */

	GALILEO_OUTL(50*1000*1000 / HZ, GT_TC0_OFS);

	GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);



	/* Enable timer */

	GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS);

	GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);



	/* Register interrupt */

	setup_irq(COBALT_GALILEO_IRQ, irq);



	/* Enable interrupt */

	GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);

	GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));

}



extern struct pci_ops gt64111_pci_ops;



static struct resource cobalt_mem_resource = {

	.start	= GT64111_MEM_BASE,

	.end	= GT64111_MEM_END,

	.start	= GT_DEF_PCI0_MEM0_BASE,

	.end	= GT_DEF_PCI0_MEM0_BASE + GT_DEF_PCI0_MEM0_SIZE - 1,

	.name	= "PCI memory",

	.flags	= IORESOURCE_MEM

};
@@ -115,7 +115,7 @@ static struct pci_controller cobalt_pci_controller = { 
	.mem_resource	= &cobalt_mem_resource,

	.mem_offset	= 0,

	.io_resource	= &cobalt_io_resource,

	.io_offset	= 0 - GT64111_IO_BASE

	.io_offset	= 0 - GT_DEF_PCI0_IO_BASE,

};



void __init plat_mem_setup(void)
@@ -128,7 +128,7 @@ void __init plat_mem_setup(void) 
	_machine_halt = cobalt_machine_halt;

	pm_power_off = cobalt_machine_power_off;



        set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE));

	set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));



	/* I/O port resource must include UART and LCD/buttons */

	ioport_resource.end = 0x0fffffff;
@@ -139,7 +139,7 @@ void __init plat_mem_setup(void) 


        /* Read the cobalt id register out of the PCI config space */

        PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3));

        cobalt_board_id = GALILEO_INL(GT_PCI0_CFGDATA_OFS);

        cobalt_board_id = GT_READ(GT_PCI0_CFGDATA_OFS);

        cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);

        cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);

arch/mips/pci/fixup-cobalt.c

+5 −6
Original line number Diff line number Diff line
@@ -94,22 +94,21 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev) 
#if 0

	if (galileo_id >= 0x10) {

		/* New Galileo, assumes PCI stop line to VIA is connected. */

		GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS);

		GT_WRITE(GT_PCI0_TOR_OFS, 0x4020);

	} else if (galileo_id == 0x1 || galileo_id == 0x2)

#endif

	{

		signed int timeo;

		/* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */

		timeo = GALILEO_INL(GT_PCI0_TOR_OFS);

		timeo = GT_READ(GT_PCI0_TOR_OFS);

		/* Old Galileo, assumes PCI STOP line to VIA is disconnected. */

		GALILEO_OUTL(

		GT_WRITE(GT_PCI0_TOR_OFS,

			(0xff << 16) |		/* retry count */

			(0xff << 8) |		/* timeout 1   */

			0xff,			/* timeout 0   */

			GT_PCI0_TOR_OFS);

			0xff);			/* timeout 0   */



		/* enable PCI retry exceeded interrupt */

		GALILEO_OUTL(GALILEO_INTR_RETRY_CTR | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);

		GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS));

	}

}

arch/mips/pci/ops-gt64111.c

+8 −8
Original line number Diff line number Diff line
@@ -38,18 +38,18 @@ static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn, 
	switch (size) {

	case 4:

		PCI_CFG_SET(devfn, where);

		*val = GALILEO_INL(GT_PCI0_CFGDATA_OFS);

		*val = GT_READ(GT_PCI0_CFGDATA_OFS);

		return PCIBIOS_SUCCESSFUL;



	case 2:

		PCI_CFG_SET(devfn, (where & ~0x3));

		*val = GALILEO_INL(GT_PCI0_CFGDATA_OFS)

		*val = GT_READ(GT_PCI0_CFGDATA_OFS)

		    >> ((where & 3) * 8);

		return PCIBIOS_SUCCESSFUL;



	case 1:

		PCI_CFG_SET(devfn, (where & ~0x3));

		*val = GALILEO_INL(GT_PCI0_CFGDATA_OFS)

		*val = GT_READ(GT_PCI0_CFGDATA_OFS)

		    >> ((where & 3) * 8);

		return PCIBIOS_SUCCESSFUL;

	}
@@ -68,25 +68,25 @@ static int gt64111_pci_write_config(struct pci_bus *bus, unsigned int devfn, 
	switch (size) {

	case 4:

		PCI_CFG_SET(devfn, where);

		GALILEO_OUTL(val, GT_PCI0_CFGDATA_OFS);

		GT_WRITE(GT_PCI0_CFGDATA_OFS, val);



		return PCIBIOS_SUCCESSFUL;



	case 2:

		PCI_CFG_SET(devfn, (where & ~0x3));

		tmp = GALILEO_INL(GT_PCI0_CFGDATA_OFS);

		tmp = GT_READ(GT_PCI0_CFGDATA_OFS);

		tmp &= ~(0xffff << ((where & 0x3) * 8));

		tmp |= (val << ((where & 0x3) * 8));

		GALILEO_OUTL(tmp, GT_PCI0_CFGDATA_OFS);

		GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);



		return PCIBIOS_SUCCESSFUL;



	case 1:

		PCI_CFG_SET(devfn, (where & ~0x3));

		tmp = GALILEO_INL(GT_PCI0_CFGDATA_OFS);

		tmp = GT_READ(GT_PCI0_CFGDATA_OFS);

		tmp &= ~(0xff << ((where & 0x3) * 8));

		tmp |= (val << ((where & 0x3) * 8));

		GALILEO_OUTL(tmp, GT_PCI0_CFGDATA_OFS);

		GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);



		return PCIBIOS_SUCCESSFUL;

	}

include/asm-mips/gt64120.h

+14 −0
Original line number Diff line number Diff line
@@ -451,6 +451,13 @@ 
#define GT_SDRAM_OPMODE_OP_MODE		3

#define GT_SDRAM_OPMODE_OP_CBR		4



#define GT_TC_CONTROL_ENTC0_SHF		0

#define GT_TC_CONTROL_ENTC0_MSK		(MSK(1) << GT_TC_CONTROL_ENTC0_SHF)

#define GT_TC_CONTROL_ENTC0_BIT		GT_TC_CONTROL_ENTC0_MSK

#define GT_TC_CONTROL_SELTC0_SHF	1

#define GT_TC_CONTROL_SELTC0_MSK	(MSK(1) << GT_TC_CONTROL_SELTC0_SHF)

#define GT_TC_CONTROL_SELTC0_BIT	GT_TC_CONTROL_SELTC0_MSK





#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF	0

#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK	(MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
@@ -523,6 +530,13 @@ 
#define GT_PCI0_CMD_SWORDSWAP_MSK	(MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)

#define GT_PCI0_CMD_SWORDSWAP_BIT	GT_PCI0_CMD_SWORDSWAP_MSK



#define GT_INTR_T0EXP_SHF		8

#define GT_INTR_T0EXP_MSK		(MSK(1) << GT_INTR_T0EXP_SHF)

#define GT_INTR_T0EXP_BIT		GT_INTR_T0EXP_MSK

#define GT_INTR_RETRYCTR0_SHF		20

#define GT_INTR_RETRYCTR0_MSK		(MSK(1) << GT_INTR_RETRYCTR0_SHF)

#define GT_INTR_RETRYCTR0_BIT		GT_INTR_RETRYCTR0_MSK



/*

 *  Misc

 */

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