Commit 56838644 authored by Manivannan Sadhasivam's avatar Manivannan Sadhasivam Committed by Shawn Guo
Browse files

arm64: dts: freescale: Add support for i.MX8QXP AI_ML board 

Add support for i.MX8QXP AI_ML board from Einfochips. This board is one
of the Consumer Edition boards of the 96Boards family based on i.MX8QXP
SoC from NXP/Freescale.

The initial support includes following peripherals which are tested and
known to be working:

1. Debug serial via UART2
2. uSD
3. WiFi
4. Ethernet

More information about this board can be found in Arrow website:
https://www.arrow.com/en/products/imx8-ai-ml/arrow-development-tools



Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: default avatarDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent b5547e22

arch/arm64/boot/dts/freescale/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -26,4 +26,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb 
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb

arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts

0 → 100644
+249 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright 2018 Einfochips

 * Copyright 2019 Linaro Ltd.

 */



/dts-v1/;



#include "imx8qxp.dtsi"



/ {

	model = "Einfochips i.MX8QXP AI_ML";

	compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";



	aliases {

		serial1 = &adma_lpuart1;

		serial2 = &adma_lpuart2;

		serial3 = &adma_lpuart3;

	};



	chosen {

		stdout-path = &adma_lpuart2;

	};



	memory@80000000 {

		device_type = "memory";

		reg = <0x00000000 0x80000000 0 0x80000000>;

	};



	leds {

		compatible = "gpio-leds";

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_leds>;



		user-led1 {

			label = "green:user1";

			gpios = <&lsio_gpio4 16 GPIO_ACTIVE_HIGH>;

			linux,default-trigger = "heartbeat";

		};



		user-led2 {

			label = "green:user2";

			gpios = <&lsio_gpio0 6 GPIO_ACTIVE_HIGH>;

			linux,default-trigger = "none";

		};



		user-led3 {

			label = "green:user3";

			gpios = <&lsio_gpio0 7 GPIO_ACTIVE_HIGH>;

			linux,default-trigger = "mmc1";

			default-state = "off";

		};



		user-led4 {

			label = "green:user4";

			gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;

			panic-indicator;

			linux,default-trigger = "none";

		};



		wlan-active-led {

			label = "yellow:wlan";

			gpios = <&lsio_gpio4 17 GPIO_ACTIVE_HIGH>;

			linux,default-trigger = "phy0tx";

			default-state = "off";

		};



		bt-active-led {

			label = "blue:bt";

			gpios = <&lsio_gpio4 18 GPIO_ACTIVE_HIGH>;

			linux,default-trigger = "hci0-power";

			default-state = "off";

		};

	};



	sdio_pwrseq: sdio-pwrseq {

		compatible = "mmc-pwrseq-simple";

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_wifi_reg_on>;

		reset-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_LOW>;

	};

};



/* BT */

&adma_lpuart0 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_lpuart0>;

	uart-has-rtscts;

	status = "okay";

};



/* LS-UART0 */

&adma_lpuart1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_lpuart1>;

	status = "okay";

};



/* Debug */

&adma_lpuart2 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_lpuart2>;

	status = "okay";

};



/* PCI-E UART */

&adma_lpuart3 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_lpuart3>;

	status = "okay";

};



&fec1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_fec1>;

	phy-mode = "rgmii-id";

	phy-handle = <&ethphy0>;

	fsl,magic-packet;

	status = "okay";



	mdio {

		#address-cells = <1>;

		#size-cells = <0>;



		ethphy0: ethernet-phy@0 {

			compatible = "ethernet-phy-ieee802.3-c22";

			reg = <0>;

		};

	};

};



/* WiFi */

&usdhc1 {

	#address-cells = <1>;

	#size-cells = <0>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc1>;

	bus-width = <4>;

	no-sd;

	non-removable;

	mmc-pwrseq = <&sdio_pwrseq>;

	status = "okay";



	brcmf: wifi@1 {

		reg = <1>;

		compatible = "brcm,bcm4329-fmac";

	};

};



/* SD */

&usdhc2 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc2>;

	bus-width = <4>;

	cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;

	status = "okay";

};



&iomuxc {

	pinctrl_fec1: fec1grp {

		fsl,pins = <

			IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000020

			IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020

			IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020

			IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x06000020

			IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020

			IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020

			IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020

			IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020

			IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x06000020

			IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020

			IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020

			IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020

			IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020

			IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020

		>;

	};



	pinctrl_leds: ledsgrp{

		fsl,pins = <

			IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06			0x00000021

			IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07			0x00000021

			IMX8QXP_EMMC0_DATA7_LSIO_GPIO4_IO16			0x00000021

			IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21			0x00000021

			IMX8QXP_EMMC0_STROBE_LSIO_GPIO4_IO17			0x00000021

			IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18			0x00000021

		>;

	};



	pinctrl_lpuart0: lpuart0grp {

		fsl,pins = <

			IMX8QXP_UART0_RX_ADMA_UART0_RX				0X06000020

			IMX8QXP_UART0_TX_ADMA_UART0_TX				0X06000020

			IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 			0x06000020

			IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B			0x06000020

		>;

	};



	pinctrl_lpuart1: lpuart1grp {

		fsl,pins = <

			IMX8QXP_UART1_RX_ADMA_UART1_RX				0X06000020

			IMX8QXP_UART1_TX_ADMA_UART1_TX				0X06000020

		>;

	};



	pinctrl_lpuart2: lpuart2grp {

		fsl,pins = <

			IMX8QXP_UART2_RX_ADMA_UART2_RX				0X06000020

			IMX8QXP_UART2_TX_ADMA_UART2_TX				0X06000020

		>;

	};



	pinctrl_lpuart3: lpuart3grp {

		fsl,pins = <

			IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX			0X06000020

			IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX			0X06000020

		>;

	};



	pinctrl_usdhc1: usdhc1grp {

		fsl,pins = <

			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041

			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD			0x00000021

			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021

			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021

			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021

			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021

		>;

	};



	pinctrl_usdhc2: usdhc2grp {

		fsl,pins = <

			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041

			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021

			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0			0x00000021

			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1			0x00000021

			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2			0x00000021

			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3			0x00000021

			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021

			IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22			0x00000021

		>;

	};



	pinctrl_wifi_reg_on: wifiregongrp {

		fsl,pins = <

			IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24			0x00000021

		>;

	};

};

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