irqchip/gic: Only allow the primary GIC to set the CPU map (567e5a01) · Commits · 戴 / test

The gic_init_bases() function initialises an array that stores the mapping between the GIC and CPUs. This array is a global array that is unconditionally initialised on every call to gic_init_bases(). Although, it is not common for there to be more than one GIC instance, there are some devices that do support nested GIC controllers and gic_init_bases() can be called more than once. A 2nd call to gic_init_bases() will clear the previous CPU mapping and will only setup the mapping again for the CPU calling gic_init_bases(). Fix this by only allowing the CPU map to be configured for the primary GIC. For secondary GICs the CPU map is not relevant because these GICs do not directly route the interrupts to the main CPU(s) but to other GICs or devices. Signed-off-by:

Jon Hunter <jonathanh@nvidia.com> Reviewed-by:

Marc Zyngier <marc.zyngier@arm.com> Cc: <linux-arm-kernel@lists.infradead.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1438332252-25248-1-git-send-email-jonathanh@nvidia.com Signed-off-by:

Thomas Gleixner <tglx@linutronix.de>

drivers/irqchip/irq-gic.c

+25 −18

Original line number	Diff line number	Diff line
		@@ -401,6 +401,12 @@ static void gic_cpu_init(struct gic_chip_data *gic)
		unsigned int cpu_mask, cpu = smp_processor_id();
		int i;

		/*
		* Setting up the CPU map is only relevant for the primary GIC
		* because any nested/secondary GICs do not directly interface
		* with the CPU(s).
		*/
		if (gic == &gic_data[0]) {
		/*
		* Get what the GIC says our CPU mask is.
		*/
		@@ -415,6 +421,7 @@ static void gic_cpu_init(struct gic_chip_data *gic)
		for (i = 0; i < NR_GIC_CPU_IF; i++)
		if (i != cpu)
		gic_cpu_map[i] &= ~cpu_mask;
		}

		gic_cpu_config(dist_base, NULL);

		@@ -925,13 +932,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
		gic_set_base_accessor(gic, gic_get_common_base);
		}

		/*
		* Initialize the CPU interface map to all CPUs.
		* It will be refined as each CPU probes its ID.
		*/
		for (i = 0; i < NR_GIC_CPU_IF; i++)
		gic_cpu_map[i] = 0xff;

		/*
		* Find out how many interrupts are supported.
		* The GIC only supports up to 1020 interrupt sources.
		@@ -977,6 +977,13 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
		return;

		if (gic_nr == 0) {
		/*
		* Initialize the CPU interface map to all CPUs.
		* It will be refined as each CPU probes its ID.
		* This is only necessary for the primary GIC.
		*/
		for (i = 0; i < NR_GIC_CPU_IF; i++)
		gic_cpu_map[i] = 0xff;
		#ifdef CONFIG_SMP
		set_smp_cross_call(gic_raise_softirq);
		register_cpu_notifier(&gic_cpu_notifier);

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