Commit 56740a71 authored by Li Yang's avatar Li Yang
Browse files

Merge tag 'soc-fsl-fix-v4.19-2' into HEAD

NXP/FSL SoC driver fixes for v4.19 round 2

- Fix crash of qman_portal by deferring its probe if qman is not probed
parents afa86d26 5a1eb8b9
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+1 −1
Original line number Diff line number Diff line
@@ -1251,7 +1251,7 @@ N: meson

ARM/Annapurna Labs ALPINE ARCHITECTURE
M:	Tsahee Zidenberg <tsahee@annapurnalabs.com>
M:	Antoine Tenart <antoine.tenart@free-electrons.com>
M:	Antoine Tenart <antoine.tenart@bootlin.com>
L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S:	Maintained
F:	arch/arm/mach-alpine/
+0 −0

File mode changed from 100755 to 100644.

+1 −0
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@@ -469,6 +469,7 @@
			ti,hwmods = "rtc";
			clocks = <&clk_32768_ck>;
			clock-names = "int-clk";
			system-power-controller;
			status = "disabled";
		};

+2 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@
#include "sama5d2-pinfunc.h"
#include <dt-bindings/mfd/atmel-flexcom.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/at91.h>

/ {
	model = "Atmel SAMA5D2 PTC EK";
@@ -299,6 +300,7 @@
							 <PIN_PA30__NWE_NANDWE>,
							 <PIN_PB2__NRD_NANDOE>;
						bias-pull-up;
						atmel,drive-strength = <ATMEL_PIO_DRVSTR_ME>;
					};

					ale_cle_rdy_cs {
+8 −6
Original line number Diff line number Diff line
@@ -106,21 +106,23 @@
		global_timer: timer@1e200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x1e200 0x20>;
			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
			interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
			clocks = <&axi_clk>;
		};

		local_timer: local-timer@1e600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x1e600 0x20>;
			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
						  IRQ_TYPE_EDGE_RISING)>;
			clocks = <&axi_clk>;
		};

		twd_watchdog: watchdog@1e620 {
			compatible = "arm,cortex-a9-twd-wdt";
			reg = <0x1e620 0x20>;
			interrupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>;
			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
						  IRQ_TYPE_LEVEL_HIGH)>;
		};

		armpll: armpll {
@@ -158,7 +160,7 @@
		serial0: serial@600 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x600 0x1b>;
			interrupts = <GIC_SPI 32 0>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&periph_clk>;
			clock-names = "periph";
			status = "disabled";
@@ -167,7 +169,7 @@
		serial1: serial@620 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x620 0x1b>;
			interrupts = <GIC_SPI 33 0>;
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&periph_clk>;
			clock-names = "periph";
			status = "disabled";
@@ -180,7 +182,7 @@
			reg = <0x2000 0x600>, <0xf0 0x10>;
			reg-names = "nand", "nand-int-base";
			status = "disabled";
			interrupts = <GIC_SPI 38 0>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "nand";
		};

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