Merge tag 'hisi-soc-dt-for-4.9' of git://github.com/hisilicon/linux-hisi into next/dt64 (5661beb3) · Commits · 戴 / test

Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt

+28 −11

Original line number	Diff line number	Diff line
		@@ -175,38 +175,55 @@ Example:
		};

		-----------------------------------------------------------------------
		Hisilicon HiP05 PCIe-SAS system controller
		Hisilicon HiP05/HiP06 PCIe-SAS sub system controller

		Required properties:
		- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
		- reg : Register address and size

		The HiP05 PCIe-SAS system controller is shared by PCIe and SAS controllers in
		HiP05 Soc to implement some basic configurations.
		The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
		HiP05 or HiP06 Soc to implement some basic configurations.

		Example:
		/* for HiP05 PCIe-SAS system */
		pcie_sas: system_controller@0xb0000000 {
		/* for HiP05 PCIe-SAS sub system */
		pcie_sas: system_controller@b0000000 {
		compatible = "hisilicon,pcie-sas-subctrl", "syscon";
		reg = <0xb0000000 0x10000>;
		};

		Hisilicon HiP05 PERISUB system controller
		Hisilicon HiP05/HiP06 PERI sub system controller

		Required properties:
		- compatible : "hisilicon,hip05-perisubc", "syscon";
		- compatible : "hisilicon,peri-subctrl", "syscon";
		- reg : Register address and size

		The HiP05 PERISUB system controller is shared by peripheral controllers in
		HiP05 Soc to implement some basic configurations. The peripheral
		The PERI sub system controller is shared by peripheral controllers in
		HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
		controllers include mdio, ddr, iic, uart, timer and so on.

		Example:
		/* for HiP05 perisub-ctrl-c system */
		/* for HiP05 sub peri system */
		peri_c_subctrl: syscon@80000000 {
		compatible = "hisilicon,hip05-perisubc", "syscon";
		compatible = "hisilicon,peri-subctrl", "syscon";
		reg = <0x0 0x80000000 0x0 0x10000>;
		};

		Hisilicon HiP05/HiP06 DSA sub system controller

		Required properties:
		- compatible : "hisilicon,dsa-subctrl", "syscon";
		- reg : Register address and size

		The DSA sub system controller is shared by peripheral controllers in
		HiP05 or HiP06 Soc to implement some basic configurations.

		Example:
		/* for HiP05 dsa sub system */
		pcie_sas: system_controller@a0000000 {
		compatible = "hisilicon,dsa-subctrl", "syscon";
		reg = <0xa0000000 0x10000>;
		};

		-----------------------------------------------------------------------
		Hisilicon CPU controller

arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts

+84 −2

Original line number	Diff line number	Diff line
		@@ -29,16 +29,56 @@
		* Reserve below regions from memory node:
		*
		* 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
		* 0x05f0,1000 - 0x05f0,1fff: Reboot reason
		* 0x06df,f000 - 0x06df,ffff: Mailbox message data
		* 0x0740,f000 - 0x0740,ffff: MCU firmware section
		* 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
		* 0x3e00,0000 - 0x3fff,ffff: OP-TEE
		*/
		memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x00000000 0x00000000 0x05e00000>,
		<0x00000000 0x05f00000 0x00000000 0x00eff000>,
		<0x00000000 0x05f00000 0x00000000 0x00001000>,
		<0x00000000 0x05f02000 0x00000000 0x00efd000>,
		<0x00000000 0x06e00000 0x00000000 0x0060f000>,
		<0x00000000 0x07410000 0x00000000 0x36bf0000>;
		<0x00000000 0x07410000 0x00000000 0x1aaf0000>,
		<0x00000000 0x22000000 0x00000000 0x1c000000>;
		};

		reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ramoops@0x21f00000 {
		compatible = "ramoops";
		reg = <0x0 0x21f00000 0x0 0x00100000>;
		record-size = <0x00020000>;
		console-size = <0x00020000>;
		ftrace-size = <0x00020000>;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
		compatible = "shared-dma-pool";
		reusable;
		size = <0x00000000 0x08000000>;
		linux,cma-default;
		};
		};

		reboot-mode-syscon@5f01000 {
		compatible = "syscon", "simple-mfd";
		reg = <0x0 0x05f01000 0x0 0x00001000>;

		reboot-mode {
		compatible = "syscon-reboot-mode";
		offset = <0x0>;

		mode-normal = <0x77665501>;
		mode-bootloader = <0x77665500>;
		mode-recovery = <0x77665502>;
		};
		};

		soc {
		@@ -55,6 +95,8 @@
		};

		uart1: uart@f7111000 {
		assigned-clocks = <&sys_ctrl HI6220_UART1_SRC>;
		assigned-clock-rates = <150000000>;
		status = "ok";
		};

		@@ -372,3 +414,43 @@
		&uart3 {
		label = "LS-UART1";
		};

		&ade {
		status = "ok";
		};

		&dsi {
		status = "ok";

		ports {
		/* 1 for output port */
		port@1 {
		reg = <1>;

		dsi_out0: endpoint@0 {
		remote-endpoint = <&adv7533_in>;
		};
		};
		};
		};

		&i2c2 {
		#address-cells = <1>;
		#size-cells = <0>;
		status = "ok";

		adv7533: adv7533@39 {
		compatible = "adi,adv7533";
		reg = <0x39>;
		interrupt-parent = <&gpio1>;
		interrupts = <1 2>;
		pd-gpio = <&gpio0 4 0>;
		adi,dsi-lanes = <4>;

		port {
		adv7533_in: endpoint {
		remote-endpoint = <&dsi_out0>;
		};
		};
		};
		};

arch/arm64/boot/dts/hisilicon/hi6220.dtsi

+61 −0

Original line number	Diff line number	Diff line
		@@ -262,6 +262,11 @@
		#clock-cells = <1>;
		};

		medianoc_ade: medianoc_ade@f4520000 {
		compatible = "syscon";
		reg = <0x0 0xf4520000 0x0 0x4000>;
		};

		stub_clock: stub_clock {
		compatible = "hisilicon,hi6220-stub-clk";
		hisilicon,hi6220-clk-sram = <&sram>;
		@@ -766,6 +771,7 @@
		interrupts = <0x0 0x48 0x4>;
		clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
		clock-names = "ciu", "biu";
		resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
		bus-width = <0x8>;
		vmmc-supply = <&ldo19>;
		pinctrl-names = "default";
		@@ -779,12 +785,16 @@
		card-detect-delay = <200>;
		hisilicon,peripheral-syscon = <&ao_ctrl>;
		cap-sd-highspeed;
		sd-uhs-sdr12;
		sd-uhs-sdr25;
		sd-uhs-sdr50;
		reg = <0x0 0xf723e000 0x0 0x1000>;
		interrupts = <0x0 0x49 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
		clock-names = "ciu", "biu";
		resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
		vqmmc-supply = <&ldo7>;
		vmmc-supply = <&ldo10>;
		bus-width = <0x4>;
		@@ -802,6 +812,7 @@
		interrupts = <0x0 0x4a 0x4>;
		clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
		clock-names = "ciu", "biu";
		resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
		bus-width = <0x4>;
		broken-cd;
		pinctrl-names = "default", "idle";
		@@ -850,5 +861,55 @@
		};
		};
		};

		ade: ade@f4100000 {
		compatible = "hisilicon,hi6220-ade";
		reg = <0x0 0xf4100000 0x0 0x7800>;
		reg-names = "ade_base";
		hisilicon,noc-syscon = <&medianoc_ade>;
		resets = <&media_ctrl MEDIA_ADE>;
		interrupts = <0 115 4>; /* ldi interrupt */

		clocks = <&media_ctrl HI6220_ADE_CORE>,
		<&media_ctrl HI6220_CODEC_JPEG>,
		<&media_ctrl HI6220_ADE_PIX_SRC>;
		/clock name/
		clock-names = "clk_ade_core",
		"clk_codec_jpeg",
		"clk_ade_pix";

		assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
		<&media_ctrl HI6220_CODEC_JPEG>;
		assigned-clock-rates = <360000000>, <288000000>;
		dma-coherent;
		status = "disabled";

		port {
		ade_out: endpoint {
		remote-endpoint = <&dsi_in>;
		};
		};
		};

		dsi: dsi@f4107800 {
		compatible = "hisilicon,hi6220-dsi";
		reg = <0x0 0xf4107800 0x0 0x100>;
		clocks = <&media_ctrl HI6220_DSI_PCLK>;
		clock-names = "pclk";
		status = "disabled";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		/* 0 for input port */
		port@0 {
		reg = <0>;
		dsi_in: endpoint {
		remote-endpoint = <&ade_out>;
		};
		};
		};
		};
		};
		};

arch/arm64/boot/dts/hisilicon/hip05.dtsi

+0 −5

Original line number	Diff line number	Diff line
		@@ -300,11 +300,6 @@
		clock-frequency = <200000000>;
		};

		peri_c_subctrl: syscon@80000000 {
		compatible = "hisilicon,hip05-perisubc", "syscon";
		reg = < 0x0 0x80000000 0x0 0x10000>;
		};

		uart0: uart@80300000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x0 0x80300000 0x0 0x10000>;

arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi

deleted100644 → 0

+0 −180

Original line number	Diff line number	Diff line
		soc0: soc@000000000 {
		#address-cells = <2>;
		#size-cells = <2>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0x0 0x0 0x0 0x1 0x0>;
		chip-id = <0>;

		soc0_mdio0: mdio@803c0000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "hisilicon,hns-mdio";
		reg = <0x0 0x803c0000 0x0 0x10000>;
		subctrl-vbase = <&peri_c_subctrl>;

		soc0_phy0: ethernet-phy@0 {
		reg = <0x0>;
		compatible = "ethernet-phy-ieee802.3-c22";
		};
		soc0_phy1: ethernet-phy@1 {
		reg = <0x1>;
		compatible = "ethernet-phy-ieee802.3-c22";
		};
		};

		dsaf0: dsa@c7000000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "hisilicon,hns-dsaf-v1";
		mode = "6port-16rss";
		interrupt-parent = <&mbigen_dsa>;

		reg = <0x0 0xc5000000 0x0 0x890000
		0x0 0xc7000000 0x0 0x60000
		>;

		reg-names = "ppe-base","dsaf-base";
		subctrl-syscon = <&dsaf_subctrl>;
		reset-field-offset = <0>;
		interrupts = <
		/* [14] ge fifo err 8 / xge 6**/
		149 0x4 150 0x4 151 0x4 152 0x4
		153 0x4 154 0x4 26 0x4 27 0x4
		155 0x4 156 0x4 157 0x4 158 0x4 159 0x4 160 0x4
		/* [12] rcb com 43*/
		0x6 0x4 0x7 0x4 0x8 0x4 0x9 0x4
		16 0x4 17 0x4 18 0x4 19 0x4
		22 0x4 23 0x4 24 0x4 25 0x4
		/* [8] ppe tnl 0-7***/
		0x0 0x4 0x1 0x4 0x2 0x4 0x3 0x4
		0x4 0x4 0x5 0x4 12 0x4 13 0x4
		/* [21] dsaf event int 3+18**/
		128 0x4 129 0x4 130 0x4
		0x83 0x4 0x84 0x4 0x85 0x4 0x86 0x4 0x87 0x4 0x88 0x4
		0x89 0x4 0x8a 0x4 0x8b 0x4 0x8c 0x4 0x8d 0x4 0x8e 0x4
		0x8f 0x4 0x90 0x4 0x91 0x4 0x92 0x4 0x93 0x4 0x94 0x4
		/* [4] debug rcb 22/
		0xe 0x1 0xf 0x1 0x14 0x1 0x15 0x1
		/* [256] sevice rcb 2128/
		0x180 0x1 0x181 0x1 0x182 0x1 0x183 0x1
		0x184 0x1 0x185 0x1 0x186 0x1 0x187 0x1
		0x188 0x1 0x189 0x1 0x18a 0x1 0x18b 0x1
		0x18c 0x1 0x18d 0x1 0x18e 0x1 0x18f 0x1
		0x190 0x1 0x191 0x1 0x192 0x1 0x193 0x1
		0x194 0x1 0x195 0x1 0x196 0x1 0x197 0x1
		0x198 0x1 0x199 0x1 0x19a 0x1 0x19b 0x1
		0x19c 0x1 0x19d 0x1 0x19e 0x1 0x19f 0x1
		0x1a0 0x1 0x1a1 0x1 0x1a2 0x1 0x1a3 0x1
		0x1a4 0x1 0x1a5 0x1 0x1a6 0x1 0x1a7 0x1
		0x1a8 0x1 0x1a9 0x1 0x1aa 0x1 0x1ab 0x1
		0x1ac 0x1 0x1ad 0x1 0x1ae 0x1 0x1af 0x1
		0x1b0 0x1 0x1b1 0x1 0x1b2 0x1 0x1b3 0x1
		0x1b4 0x1 0x1b5 0x1 0x1b6 0x1 0x1b7 0x1
		0x1b8 0x1 0x1b9 0x1 0x1ba 0x1 0x1bb 0x1
		0x1bc 0x1 0x1bd 0x1 0x1be 0x1 0x1bf 0x1
		0x1c0 0x1 0x1c1 0x1 0x1c2 0x1 0x1c3 0x1
		0x1c4 0x1 0x1c5 0x1 0x1c6 0x1 0x1c7 0x1
		0x1c8 0x1 0x1c9 0x1 0x1ca 0x1 0x1cb 0x1
		0x1cc 0x1 0x1cd 0x1 0x1ce 0x1 0x1cf 0x1
		0x1d0 0x1 0x1d1 0x1 0x1d2 0x1 0x1d3 0x1
		0x1d4 0x1 0x1d5 0x1 0x1d6 0x1 0x1d7 0x1
		0x1d8 0x1 0x1d9 0x1 0x1da 0x1 0x1db 0x1
		0x1dc 0x1 0x1dd 0x1 0x1de 0x1 0x1df 0x1
		0x1e0 0x1 0x1e1 0x1 0x1e2 0x1 0x1e3 0x1
		0x1e4 0x1 0x1e5 0x1 0x1e6 0x1 0x1e7 0x1
		0x1e8 0x1 0x1e9 0x1 0x1ea 0x1 0x1eb 0x1
		0x1ec 0x1 0x1ed 0x1 0x1ee 0x1 0x1ef 0x1
		0x1f0 0x1 0x1f1 0x1 0x1f2 0x1 0x1f3 0x1
		0x1f4 0x1 0x1f5 0x1 0x1f6 0x1 0x1f7 0x1
		0x1f8 0x1 0x1f9 0x1 0x1fa 0x1 0x1fb 0x1
		0x1fc 0x1 0x1fd 0x1 0x1fe 0x1 0x1ff 0x1
		0x200 0x1 0x201 0x1 0x202 0x1 0x203 0x1
		0x204 0x1 0x205 0x1 0x206 0x1 0x207 0x1
		0x208 0x1 0x209 0x1 0x20a 0x1 0x20b 0x1
		0x20c 0x1 0x20d 0x1 0x20e 0x1 0x20f 0x1
		0x210 0x1 0x211 0x1 0x212 0x1 0x213 0x1
		0x214 0x1 0x215 0x1 0x216 0x1 0x217 0x1
		0x218 0x1 0x219 0x1 0x21a 0x1 0x21b 0x1
		0x21c 0x1 0x21d 0x1 0x21e 0x1 0x21f 0x1
		0x220 0x1 0x221 0x1 0x222 0x1 0x223 0x1
		0x224 0x1 0x225 0x1 0x226 0x1 0x227 0x1
		0x228 0x1 0x229 0x1 0x22a 0x1 0x22b 0x1
		0x22c 0x1 0x22d 0x1 0x22e 0x1 0x22f 0x1
		0x230 0x1 0x231 0x1 0x232 0x1 0x233 0x1
		0x234 0x1 0x235 0x1 0x236 0x1 0x237 0x1
		0x238 0x1 0x239 0x1 0x23a 0x1 0x23b 0x1
		0x23c 0x1 0x23d 0x1 0x23e 0x1 0x23f 0x1
		0x240 0x1 0x241 0x1 0x242 0x1 0x243 0x1
		0x244 0x1 0x245 0x1 0x246 0x1 0x247 0x1
		0x248 0x1 0x249 0x1 0x24a 0x1 0x24b 0x1
		0x24c 0x1 0x24d 0x1 0x24e 0x1 0x24f 0x1
		0x250 0x1 0x251 0x1 0x252 0x1 0x253 0x1
		0x254 0x1 0x255 0x1 0x256 0x1 0x257 0x1
		0x258 0x1 0x259 0x1 0x25a 0x1 0x25b 0x1
		0x25c 0x1 0x25d 0x1 0x25e 0x1 0x25f 0x1
		0x260 0x1 0x261 0x1 0x262 0x1 0x263 0x1
		0x264 0x1 0x265 0x1 0x266 0x1 0x267 0x1
		0x268 0x1 0x269 0x1 0x26a 0x1 0x26b 0x1
		0x26c 0x1 0x26d 0x1 0x26e 0x1 0x26f 0x1
		0x270 0x1 0x271 0x1 0x272 0x1 0x273 0x1
		0x274 0x1 0x275 0x1 0x276 0x1 0x277 0x1
		0x278 0x1 0x279 0x1 0x27a 0x1 0x27b 0x1
		0x27c 0x1 0x27d 0x1 0x27e 0x1 0x27f 0x1>;
		buf-size = <4096>;
		desc-num = <1024>;
		dma-coherent;

		port@0 {
		reg = <0>;
		serdes-syscon = <&serdes_ctrl0>;
		};
		port@1 {
		reg = <1>;
		serdes-syscon = <&serdes_ctrl0>;
		};
		port@4 {
		reg = <4>;
		phy-handle = <&soc0_phy0>;
		serdes-syscon = <&serdes_ctrl1>;
		};
		port@5 {
		reg = <5>;
		phy-handle = <&soc0_phy1>;
		serdes-syscon = <&serdes_ctrl1>;
		};
		};

		eth0: ethernet@0{
		compatible = "hisilicon,hns-nic-v1";
		ae-handle = <&dsaf0>;
		port-idx-in-ae = <0>;
		local-mac-address = [00 00 00 01 00 58];
		status = "disabled";
		dma-coherent;
		};
		eth1: ethernet@1{
		compatible = "hisilicon,hns-nic-v1";
		ae-handle = <&dsaf0>;
		port-idx-in-ae = <1>;
		local-mac-address = [00 00 00 01 00 59];
		status = "disabled";
		dma-coherent;
		};
		eth2: ethernet@4{
		compatible = "hisilicon,hns-nic-v1";
		ae-handle = <&dsaf0>;
		port-idx-in-ae = <4>;
		local-mac-address = [00 00 00 01 00 5a];
		status = "disabled";
		dma-coherent;
		};
		eth3: ethernet@5{
		compatible = "hisilicon,hns-nic-v1";
		ae-handle = <&dsaf0>;
		port-idx-in-ae = <5>;
		local-mac-address = [00 00 00 01 00 5b];
		status = "disabled";
		dma-coherent;
		};
		};

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