Commit 565f499c authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'bnx2x-Perform-IdleChk-dump' 



Sudarsana Reddy Kalluru says:

====================
bnx2x: Perform IdleChk dump.

Idlechk test verifies that the chip is in idle state. If there are any
errors, Idlechk dump would capture the same. This data will help in
debugging the device related issues.
The patch series adds driver support for dumping IdleChk data during the
debug dump collection.
Patch (1) adds register definitions required in this implementation.
Patch (2) adds the implementation for Idlechk tests.
Patch (3) adds driver changes to invoke Idlechk implementation.

Changes from previous version:
-------------------------------
v3: Combined the test data creation and implementation to a single patch.
v2: Addressed issues reported by kernel test robot.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents f91c031e a4666570

drivers/net/ethernet/broadcom/bnx2x/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -5,5 +5,5 @@ 


obj-$(CONFIG_BNX2X) += bnx2x.o



bnx2x-y := bnx2x_main.o bnx2x_link.o bnx2x_cmn.o bnx2x_ethtool.o bnx2x_stats.o bnx2x_dcb.o bnx2x_sp.o

bnx2x-y := bnx2x_main.o bnx2x_link.o bnx2x_cmn.o bnx2x_ethtool.o bnx2x_stats.o bnx2x_dcb.o bnx2x_sp.o bnx2x_self_test.o

bnx2x-$(CONFIG_BNX2X_SRIOV) += bnx2x_vfpf.o bnx2x_sriov.o

drivers/net/ethernet/broadcom/bnx2x/bnx2x.h

+3 −7
Original line number Diff line number Diff line
@@ -1979,6 +1979,9 @@ struct bnx2x_func_init_params { 


#define skip_queue(bp, idx)	(NO_FCOE(bp) && IS_FCOE_IDX(idx))



/*self test*/

int bnx2x_idle_chk(struct bnx2x *bp);



/**

 * bnx2x_set_mac_one - configure a single MAC address

 *
@@ -2430,13 +2433,6 @@ int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err); 
#define HC_SEG_ACCESS_ATTN		4

#define HC_SEG_ACCESS_NORM		0   /*Driver decision 0-1*/



static const u32 dmae_reg_go_c[] = {

	DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,

	DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,

	DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,

	DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15

};



void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev);

void bnx2x_notify_link_changed(struct bnx2x *bp);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

+16 −0
Original line number Diff line number Diff line
@@ -276,6 +276,13 @@ static const struct pci_device_id bnx2x_pci_tbl[] = { 


MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);



const u32 dmae_reg_go_c[] = {

	DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,

	DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,

	DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,

	DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15

};



/* Global resources for unloading a previously loaded device */

#define BNX2X_PREV_WAIT_NEEDED 1

static DEFINE_SEMAPHORE(bnx2x_prev_sem);
@@ -1169,9 +1176,18 @@ void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int) 
	}

#endif

	if (IS_PF(bp)) {

		int tmp_msg_en = bp->msg_enable;



		bnx2x_fw_dump(bp);

		bp->msg_enable |= NETIF_MSG_HW;

		BNX2X_ERR("Idle check (1st round) ----------\n");

		bnx2x_idle_chk(bp);

		BNX2X_ERR("Idle check (2nd round) ----------\n");

		bnx2x_idle_chk(bp);

		bp->msg_enable = tmp_msg_en;

		bnx2x_mc_assert(bp);

	}



	BNX2X_ERR("end crash dump -----------------\n");

}

drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h

+76 −2
Original line number Diff line number Diff line
@@ -7639,6 +7639,82 @@ Theotherbitsarereservedandshouldbezero*/ 
	(0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))

#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)



/* IdleChk registers */

#define PXP_REG_HST_VF_DISABLED_ERROR_VALID			 0x1030bc

#define PXP_REG_HST_VF_DISABLED_ERROR_DATA			 0x1030b8

#define PXP_REG_HST_PER_VIOLATION_VALID				 0x1030e0

#define PXP_REG_HST_INCORRECT_ACCESS_VALID			 0x1030cc

#define PXP2_REG_RD_CPL_ERR_DETAILS				 0x120778

#define PXP2_REG_RD_CPL_ERR_DETAILS2				 0x12077c

#define PXP2_REG_RQ_GARB					 0x120748

#define PBF_REG_DISABLE_NEW_TASK_PROC_Q0			 0x15c1bc

#define PBF_REG_DISABLE_NEW_TASK_PROC_Q1			 0x15c1c0

#define PBF_REG_DISABLE_NEW_TASK_PROC_Q2			 0x15c1c4

#define PBF_REG_DISABLE_NEW_TASK_PROC_Q3			 0x15c1c8

#define PBF_REG_DISABLE_NEW_TASK_PROC_Q4			 0x15c1cc

#define PBF_REG_DISABLE_NEW_TASK_PROC_Q5			 0x15c1d0

#define PBF_REG_CREDIT_Q2					 0x140344

#define PBF_REG_CREDIT_Q3					 0x140348

#define PBF_REG_CREDIT_Q4					 0x14034c

#define PBF_REG_CREDIT_Q5					 0x140350

#define PBF_REG_INIT_CRD_Q2					 0x15c238

#define PBF_REG_INIT_CRD_Q3					 0x15c23c

#define PBF_REG_INIT_CRD_Q4					 0x15c240

#define PBF_REG_INIT_CRD_Q5					 0x15c244

#define PBF_REG_TASK_CNT_Q0					 0x140374

#define PBF_REG_TASK_CNT_Q1					 0x140378

#define PBF_REG_TASK_CNT_Q2					 0x14037c

#define PBF_REG_TASK_CNT_Q3					 0x140380

#define PBF_REG_TASK_CNT_Q4					 0x140384

#define PBF_REG_TASK_CNT_Q5					 0x140388

#define PBF_REG_TASK_CNT_LB_Q					 0x140370

#define QM_REG_BYTECRD0						 0x16e6fc

#define QM_REG_BYTECRD1						 0x16e700

#define QM_REG_BYTECRD2						 0x16e704

#define QM_REG_BYTECRD3						 0x16e7ac

#define QM_REG_BYTECRD4						 0x16e7b0

#define QM_REG_BYTECRD5						 0x16e7b4

#define QM_REG_BYTECRD6						 0x16e7b8

#define QM_REG_BYTECRDCMDQ_0					 0x16e6e8

#define QM_REG_BYTECRDERRREG					 0x16e708

#define MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID			 0xa714

#define QM_REG_VOQCREDIT_2					 0x1682d8

#define QM_REG_VOQCREDIT_3					 0x1682dc

#define QM_REG_VOQCREDIT_5					 0x1682e4

#define QM_REG_VOQCREDIT_6					 0x1682e8

#define QM_REG_VOQINITCREDIT_3					 0x16806c

#define QM_REG_VOQINITCREDIT_6					 0x168078

#define QM_REG_FWVOQ0TOHWVOQ					 0x16e7bc

#define QM_REG_FWVOQ1TOHWVOQ					 0x16e7c0

#define QM_REG_FWVOQ2TOHWVOQ					 0x16e7c4

#define QM_REG_FWVOQ3TOHWVOQ					 0x16e7c8

#define QM_REG_FWVOQ4TOHWVOQ					 0x16e7cc

#define QM_REG_FWVOQ5TOHWVOQ					 0x16e7d0

#define QM_REG_FWVOQ6TOHWVOQ					 0x16e7d4

#define QM_REG_FWVOQ7TOHWVOQ					 0x16e7d8

#define NIG_REG_INGRESS_EOP_PORT0_EMPTY				 0x104ec

#define NIG_REG_INGRESS_EOP_PORT1_EMPTY				 0x104f8

#define NIG_REG_INGRESS_RMP0_DSCR_EMPTY				 0x10530

#define NIG_REG_INGRESS_RMP1_DSCR_EMPTY				 0x10538

#define NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY			 0x10508

#define NIG_REG_EGRESS_MNG0_FIFO_EMPTY				 0x10460

#define NIG_REG_EGRESS_MNG1_FIFO_EMPTY				 0x10474

#define NIG_REG_EGRESS_DEBUG_FIFO_EMPTY				 0x10418

#define NIG_REG_EGRESS_DELAY0_EMPTY				 0x10420

#define NIG_REG_EGRESS_DELAY1_EMPTY				 0x10428

#define NIG_REG_LLH0_FIFO_EMPTY					 0x10548

#define NIG_REG_LLH1_FIFO_EMPTY					 0x10558

#define NIG_REG_P0_TX_MNG_HOST_FIFO_EMPTY			 0x182a8

#define NIG_REG_P0_TLLH_FIFO_EMPTY				 0x18308

#define NIG_REG_P0_HBUF_DSCR_EMPTY				 0x18318

#define NIG_REG_P1_HBUF_DSCR_EMPTY				 0x18348

#define NIG_REG_P0_RX_MACFIFO_EMPTY				 0x18570

#define NIG_REG_P0_TX_MACFIFO_EMPTY				 0x18578

#define NIG_REG_EGRESS_DELAY2_EMPTY				 0x1862c

#define NIG_REG_EGRESS_DELAY3_EMPTY				 0x18630

#define NIG_REG_EGRESS_DELAY4_EMPTY				 0x18634

#define NIG_REG_EGRESS_DELAY5_EMPTY				 0x18638



/******************************************************************************

 * Description:

 *	   Calculates crc 8 on a word value: polynomial 0-1-2-8
@@ -7697,6 +7773,4 @@ static inline u8 calc_crc8(u32 data, u8 crc) 


	return crc_res;

}





#endif /* BNX2X_REG_H */

drivers/net/ethernet/broadcom/bnx2x/bnx2x_self_test.c

0 → 100644
+3183 −0

File added.

Preview size limit exceeded, changes collapsed.

CRA Git | Maintained and supported by SUSTech CRA and CCSE