Commit 564c836f authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer
Browse files

MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT 



Commit 930beb5a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot
to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non
coherent DMA because of a wrong allocation alignment.

Fixes: 930beb5a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>")
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent baf5cb30

arch/mips/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -877,6 +877,7 @@ config SNI_RM 
	select I8253

	select I8259

	select ISA

	select MIPS_L1_CACHE_SHIFT_6

	select SWAP_IO_SPACE if CPU_BIG_ENDIAN

	select SYS_HAS_CPU_R4X00

	select SYS_HAS_CPU_R5000

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