Commit 56425638 authored Feb 15, 2019 by Maxime Chevallier Committed by David S. Miller Feb 17, 2019

net: phy: marvell10g: Don't explicitly set Pause and Asym_Pause



The PHY core expects PHY drivers not to set Pause and Asym_Pause bits,
unless the driver only wants to specify one of them due to HW
limitation. In the case of the Marvell10g driver, we don't need to set
them.

Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Suggested-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

parent a0bc653b

drivers/net/phy/marvell10g.c

+0 −3

Original line number	Diff line number	Diff line
		@@ -242,9 +242,6 @@ static int mv3310_config_init(struct phy_device *phydev)
		phydev->interface != PHY_INTERFACE_MODE_10GKR)
		return -ENODEV;

		__set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
		__set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);

		if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) {
		val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
		if (val < 0)

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