iavf: rename most of i40e strings (56184e01) · Commits · 戴 / test

drivers/net/ethernet/intel/iavf/i40e_adminq.c

+49 −49

Original line number	Diff line number	Diff line
		@@ -36,7 +36,7 @@ static iavf_status i40e_alloc_adminq_asq_ring(struct iavf_hw *hw)
		{
		iavf_status ret_code;

		ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
		ret_code = iavf_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
		i40e_mem_atq_ring,
		(hw->aq.num_asq_entries *
		sizeof(struct i40e_aq_desc)),
		@@ -44,11 +44,11 @@ static iavf_status i40e_alloc_adminq_asq_ring(struct iavf_hw *hw)
		if (ret_code)
		return ret_code;

		ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
		ret_code = iavf_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
		(hw->aq.num_asq_entries *
		sizeof(struct i40e_asq_cmd_details)));
		if (ret_code) {
		i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
		iavf_free_dma_mem(hw, &hw->aq.asq.desc_buf);
		return ret_code;
		}

		@@ -63,7 +63,7 @@ static iavf_status i40e_alloc_adminq_arq_ring(struct iavf_hw *hw)
		{
		iavf_status ret_code;

		ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
		ret_code = iavf_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
		i40e_mem_arq_ring,
		(hw->aq.num_arq_entries *
		sizeof(struct i40e_aq_desc)),
		@@ -81,7 +81,7 @@ static iavf_status i40e_alloc_adminq_arq_ring(struct iavf_hw *hw)
		**/
		static void i40e_free_adminq_asq(struct iavf_hw *hw)
		{
		i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
		iavf_free_dma_mem(hw, &hw->aq.asq.desc_buf);
		}

		/**
		@@ -93,7 +93,7 @@ static void i40e_free_adminq_asq(struct iavf_hw *hw)
		**/
		static void i40e_free_adminq_arq(struct iavf_hw *hw)
		{
		i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
		iavf_free_dma_mem(hw, &hw->aq.arq.desc_buf);
		}

		/**
		@@ -103,7 +103,7 @@ static void i40e_free_adminq_arq(struct iavf_hw *hw)
		static iavf_status i40e_alloc_arq_bufs(struct iavf_hw *hw)
		{
		struct i40e_aq_desc *desc;
		struct i40e_dma_mem *bi;
		struct iavf_dma_mem *bi;
		iavf_status ret_code;
		int i;

		@@ -112,17 +112,17 @@ static iavf_status i40e_alloc_arq_bufs(struct iavf_hw *hw)
		*/

		/* buffer_info structures do not need alignment */
		ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
		ret_code = iavf_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
		(hw->aq.num_arq_entries *
		sizeof(struct i40e_dma_mem)));
		sizeof(struct iavf_dma_mem)));
		if (ret_code)
		goto alloc_arq_bufs;
		hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;
		hw->aq.arq.r.arq_bi = (struct iavf_dma_mem *)hw->aq.arq.dma_head.va;

		/* allocate the mapped buffers */
		for (i = 0; i < hw->aq.num_arq_entries; i++) {
		bi = &hw->aq.arq.r.arq_bi[i];
		ret_code = i40e_allocate_dma_mem(hw, bi,
		ret_code = iavf_allocate_dma_mem(hw, bi,
		i40e_mem_arq_buf,
		hw->aq.arq_buf_size,
		IAVF_ADMINQ_DESC_ALIGNMENT);
		@@ -158,8 +158,8 @@ unwind_alloc_arq_bufs:
		/* don't try to free the one that failed... */
		i--;
		for (; i >= 0; i--)
		i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
		i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
		iavf_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
		iavf_free_virt_mem(hw, &hw->aq.arq.dma_head);

		return ret_code;
		}
		@@ -170,22 +170,22 @@ unwind_alloc_arq_bufs:
		**/
		static iavf_status i40e_alloc_asq_bufs(struct iavf_hw *hw)
		{
		struct i40e_dma_mem *bi;
		struct iavf_dma_mem *bi;
		iavf_status ret_code;
		int i;

		/* No mapped memory needed yet, just the buffer info structures */
		ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
		ret_code = iavf_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
		(hw->aq.num_asq_entries *
		sizeof(struct i40e_dma_mem)));
		sizeof(struct iavf_dma_mem)));
		if (ret_code)
		goto alloc_asq_bufs;
		hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;
		hw->aq.asq.r.asq_bi = (struct iavf_dma_mem *)hw->aq.asq.dma_head.va;

		/* allocate the mapped buffers */
		for (i = 0; i < hw->aq.num_asq_entries; i++) {
		bi = &hw->aq.asq.r.asq_bi[i];
		ret_code = i40e_allocate_dma_mem(hw, bi,
		ret_code = iavf_allocate_dma_mem(hw, bi,
		i40e_mem_asq_buf,
		hw->aq.asq_buf_size,
		IAVF_ADMINQ_DESC_ALIGNMENT);
		@@ -199,8 +199,8 @@ unwind_alloc_asq_bufs:
		/* don't try to free the one that failed... */
		i--;
		for (; i >= 0; i--)
		i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
		i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
		iavf_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
		iavf_free_virt_mem(hw, &hw->aq.asq.dma_head);

		return ret_code;
		}
		@@ -215,13 +215,13 @@ static void i40e_free_arq_bufs(struct iavf_hw *hw)

		/* free descriptors */
		for (i = 0; i < hw->aq.num_arq_entries; i++)
		i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
		iavf_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);

		/* free the descriptor memory */
		i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
		iavf_free_dma_mem(hw, &hw->aq.arq.desc_buf);

		/* free the dma header */
		i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
		iavf_free_virt_mem(hw, &hw->aq.arq.dma_head);
		}

		/**
		@@ -235,16 +235,16 @@ static void i40e_free_asq_bufs(struct iavf_hw *hw)
		/* only unmap if the address is non-NULL */
		for (i = 0; i < hw->aq.num_asq_entries; i++)
		if (hw->aq.asq.r.asq_bi[i].pa)
		i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
		iavf_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);

		/* free the buffer info list */
		i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
		iavf_free_virt_mem(hw, &hw->aq.asq.cmd_buf);

		/* free the descriptor memory */
		i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
		iavf_free_dma_mem(hw, &hw->aq.asq.desc_buf);

		/* free the dma header */
		i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
		iavf_free_virt_mem(hw, &hw->aq.asq.dma_head);
		}

		/**
		@@ -570,7 +570,7 @@ iavf_status iavf_shutdown_adminq(struct iavf_hw *hw)
		**/
		static u16 i40e_clean_asq(struct iavf_hw *hw)
		{
		struct i40e_adminq_ring *asq = &hw->aq.asq;
		struct iavf_adminq_ring *asq = &hw->aq.asq;
		struct i40e_asq_cmd_details *details;
		u16 ntc = asq->next_to_clean;
		struct i40e_aq_desc desc_cb;
		@@ -579,7 +579,7 @@ static u16 i40e_clean_asq(struct iavf_hw *hw)
		desc = IAVF_ADMINQ_DESC(*asq, ntc);
		details = I40E_ADMINQ_DETAILS(*asq, ntc);
		while (rd32(hw, hw->aq.asq.head) != ntc) {
		iavf_debug(hw, I40E_DEBUG_AQ_MESSAGE,
		iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
		"ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));

		if (details->callback) {
		@@ -600,7 +600,7 @@ static u16 i40e_clean_asq(struct iavf_hw *hw)

		asq->next_to_clean = ntc;

		return I40E_DESC_UNUSED(asq);
		return IAVF_DESC_UNUSED(asq);
		}

		/**
		@@ -634,18 +634,18 @@ iavf_status iavf_asq_send_command(struct iavf_hw hw, struct i40e_aq_desc desc,
		u16 buff_size,
		struct i40e_asq_cmd_details *cmd_details)
		{
		iavf_status status = 0;
		struct i40e_dma_mem *dma_buff = NULL;
		struct iavf_dma_mem *dma_buff = NULL;
		struct i40e_asq_cmd_details *details;
		struct i40e_aq_desc *desc_on_ring;
		bool cmd_completed = false;
		iavf_status status = 0;
		u16 retval = 0;
		u32 val = 0;

		mutex_lock(&hw->aq.asq_mutex);

		if (hw->aq.asq.count == 0) {
		iavf_debug(hw, I40E_DEBUG_AQ_MESSAGE,
		iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
		"AQTX: Admin queue not initialized.\n");
		status = I40E_ERR_QUEUE_EMPTY;
		goto asq_send_command_error;
		@@ -655,7 +655,7 @@ iavf_status iavf_asq_send_command(struct iavf_hw hw, struct i40e_aq_desc desc,

		val = rd32(hw, hw->aq.asq.head);
		if (val >= hw->aq.num_asq_entries) {
		iavf_debug(hw, I40E_DEBUG_AQ_MESSAGE,
		iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
		"AQTX: head overrun at %d\n", val);
		status = I40E_ERR_QUEUE_EMPTY;
		goto asq_send_command_error;
		@@ -685,7 +685,7 @@ iavf_status iavf_asq_send_command(struct iavf_hw hw, struct i40e_aq_desc desc,

		if (buff_size > hw->aq.asq_buf_size) {
		iavf_debug(hw,
		I40E_DEBUG_AQ_MESSAGE,
		IAVF_DEBUG_AQ_MESSAGE,
		"AQTX: Invalid buffer size: %d.\n",
		buff_size);
		status = I40E_ERR_INVALID_SIZE;
		@@ -694,7 +694,7 @@ iavf_status iavf_asq_send_command(struct iavf_hw hw, struct i40e_aq_desc desc,

		if (details->postpone && !details->async) {
		iavf_debug(hw,
		I40E_DEBUG_AQ_MESSAGE,
		IAVF_DEBUG_AQ_MESSAGE,
		"AQTX: Async flag not set along with postpone flag");
		status = I40E_ERR_PARAM;
		goto asq_send_command_error;
		@@ -709,7 +709,7 @@ iavf_status iavf_asq_send_command(struct iavf_hw hw, struct i40e_aq_desc desc,
		*/
		if (i40e_clean_asq(hw) == 0) {
		iavf_debug(hw,
		I40E_DEBUG_AQ_MESSAGE,
		IAVF_DEBUG_AQ_MESSAGE,
		"AQTX: Error queue is full.\n");
		status = I40E_ERR_ADMIN_QUEUE_FULL;
		goto asq_send_command_error;
		@@ -738,8 +738,8 @@ iavf_status iavf_asq_send_command(struct iavf_hw hw, struct i40e_aq_desc desc,
		}

		/* bump the tail */
		iavf_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
		iavf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring,
		iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
		iavf_debug_aq(hw, IAVF_DEBUG_AQ_COMMAND, (void *)desc_on_ring,
		buff, buff_size);
		(hw->aq.asq.next_to_use)++;
		if (hw->aq.asq.next_to_use == hw->aq.asq.count)
		@@ -772,7 +772,7 @@ iavf_status iavf_asq_send_command(struct iavf_hw hw, struct i40e_aq_desc desc,
		retval = le16_to_cpu(desc->retval);
		if (retval != 0) {
		iavf_debug(hw,
		I40E_DEBUG_AQ_MESSAGE,
		IAVF_DEBUG_AQ_MESSAGE,
		"AQTX: Command completed with error 0x%X.\n",
		retval);

		@@ -789,9 +789,9 @@ iavf_status iavf_asq_send_command(struct iavf_hw hw, struct i40e_aq_desc desc,
		hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
		}

		iavf_debug(hw, I40E_DEBUG_AQ_MESSAGE,
		iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
		"AQTX: desc and buffer writeback:\n");
		iavf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size);
		iavf_debug_aq(hw, IAVF_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size);

		/* save writeback aq if requested */
		if (details->wb_desc)
		@@ -801,11 +801,11 @@ iavf_status iavf_asq_send_command(struct iavf_hw hw, struct i40e_aq_desc desc,
		if ((!cmd_completed) &&
		(!details->async && !details->postpone)) {
		if (rd32(hw, hw->aq.asq.len) & IAVF_VF_ATQLEN1_ATQCRIT_MASK) {
		iavf_debug(hw, I40E_DEBUG_AQ_MESSAGE,
		iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
		"AQTX: AQ Critical error.\n");
		status = I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR;
		} else {
		iavf_debug(hw, I40E_DEBUG_AQ_MESSAGE,
		iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
		"AQTX: Writeback timeout.\n");
		status = I40E_ERR_ADMIN_QUEUE_TIMEOUT;
		}
		@@ -848,7 +848,7 @@ iavf_status iavf_clean_arq_element(struct iavf_hw *hw,
		u16 ntc = hw->aq.arq.next_to_clean;
		struct i40e_aq_desc *desc;
		iavf_status ret_code = 0;
		struct i40e_dma_mem *bi;
		struct iavf_dma_mem *bi;
		u16 desc_idx;
		u16 datalen;
		u16 flags;
		@@ -861,7 +861,7 @@ iavf_status iavf_clean_arq_element(struct iavf_hw *hw,
		mutex_lock(&hw->aq.arq_mutex);

		if (hw->aq.arq.count == 0) {
		iavf_debug(hw, I40E_DEBUG_AQ_MESSAGE,
		iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
		"AQRX: Admin queue not initialized.\n");
		ret_code = I40E_ERR_QUEUE_EMPTY;
		goto clean_arq_element_err;
		@@ -885,7 +885,7 @@ iavf_status iavf_clean_arq_element(struct iavf_hw *hw,
		if (flags & I40E_AQ_FLAG_ERR) {
		ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
		iavf_debug(hw,
		I40E_DEBUG_AQ_MESSAGE,
		IAVF_DEBUG_AQ_MESSAGE,
		"AQRX: Event received with error 0x%X.\n",
		hw->aq.arq_last_status);
		}
		@@ -897,8 +897,8 @@ iavf_status iavf_clean_arq_element(struct iavf_hw *hw,
		memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va,
		e->msg_len);

		iavf_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
		iavf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,
		iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
		iavf_debug_aq(hw, IAVF_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,
		hw->aq.arq_buf_size);

		/* Restore the original datalen and buffer address in the desc,

drivers/net/ethernet/intel/iavf/i40e_adminq.h

+12 −12

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0 */
		/* Copyright(c) 2013 - 2018 Intel Corporation. */

		#ifndef _I40E_ADMINQ_H_
		#define _I40E_ADMINQ_H_
		#ifndef _IAVF_ADMINQ_H_
		#define _IAVF_ADMINQ_H_

		#include "i40e_osdep.h"
		#include "i40e_status.h"
		@@ -13,14 +13,14 @@

		#define IAVF_ADMINQ_DESC_ALIGNMENT 4096

		struct i40e_adminq_ring {
		struct i40e_virt_mem dma_head; /* space for dma structures */
		struct i40e_dma_mem desc_buf; /* descriptor ring memory */
		struct i40e_virt_mem cmd_buf; /* command buffer memory */
		struct iavf_adminq_ring {
		struct iavf_virt_mem dma_head; /* space for dma structures */
		struct iavf_dma_mem desc_buf; /* descriptor ring memory */
		struct iavf_virt_mem cmd_buf; /* command buffer memory */

		union {
		struct i40e_dma_mem *asq_bi;
		struct i40e_dma_mem *arq_bi;
		struct iavf_dma_mem *asq_bi;
		struct iavf_dma_mem *arq_bi;
		} r;

		u16 count; /* Number of descriptors */
		@@ -61,9 +61,9 @@ struct i40e_arq_event_info {
		};

		/* Admin Queue information */
		struct i40e_adminq_info {
		struct i40e_adminq_ring arq; /* receive queue */
		struct i40e_adminq_ring asq; /* send queue */
		struct iavf_adminq_info {
		struct iavf_adminq_ring arq; /* receive queue */
		struct iavf_adminq_ring asq; /* send queue */
		u32 asq_cmd_timeout; /* send queue cmd write back timeout*/
		u16 num_arq_entries; /* receive queue depth */
		u16 num_asq_entries; /* send queue depth */
		@@ -132,4 +132,4 @@ static inline int i40e_aq_rc_to_posix(int aq_ret, int aq_rc)

		void iavf_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc, u16 opcode);

		#endif /* _I40E_ADMINQ_H_ */
		#endif /* _IAVF_ADMINQ_H_ */

drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h

+3 −1

Original line number	Diff line number	Diff line
		@@ -5,7 +5,9 @@
		#define _I40E_ADMINQ_CMD_H_

		/* This header file defines the i40e Admin Queue commands and is shared between
		* i40e Firmware and Software.
		* i40e Firmware and Software. Do not change the names in this file to IAVF
		* because this file should be diff-able against the i40e version, even
		* though many parts have been removed in this VF version.
		*
		* This file needs to comply with the Linux Kernel coding style.
		*/

drivers/net/ethernet/intel/iavf/i40e_alloc.h

+19 −19

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0 */
		/* Copyright(c) 2013 - 2018 Intel Corporation. */

		#ifndef _I40E_ALLOC_H_
		#define _I40E_ALLOC_H_
		#ifndef _IAVF_ALLOC_H_
		#define _IAVF_ALLOC_H_

		struct iavf_hw;

		/* Memory allocation types */
		enum i40e_memory_type {
		i40e_mem_arq_buf = 0, /* ARQ indirect command buffer */
		i40e_mem_asq_buf = 1,
		i40e_mem_atq_buf = 2, /* ATQ indirect command buffer */
		i40e_mem_arq_ring = 3, /* ARQ descriptor ring */
		i40e_mem_atq_ring = 4, /* ATQ descriptor ring */
		i40e_mem_pd = 5, /* Page Descriptor */
		i40e_mem_bp = 6, /* Backing Page - 4KB */
		i40e_mem_bp_jumbo = 7, /* Backing Page - > 4KB */
		i40e_mem_reserved
		enum iavf_memory_type {
		iavf_mem_arq_buf = 0, /* ARQ indirect command buffer */
		iavf_mem_asq_buf = 1,
		iavf_mem_atq_buf = 2, /* ATQ indirect command buffer */
		iavf_mem_arq_ring = 3, /* ARQ descriptor ring */
		iavf_mem_atq_ring = 4, /* ATQ descriptor ring */
		iavf_mem_pd = 5, /* Page Descriptor */
		iavf_mem_bp = 6, /* Backing Page - 4KB */
		iavf_mem_bp_jumbo = 7, /* Backing Page - > 4KB */
		iavf_mem_reserved
		};

		/* prototype for functions used for dynamic memory allocation */
		iavf_status i40e_allocate_dma_mem(struct iavf_hw hw, struct i40e_dma_mem mem,
		enum i40e_memory_type type,
		iavf_status iavf_allocate_dma_mem(struct iavf_hw hw, struct iavf_dma_mem mem,
		enum iavf_memory_type type,
		u64 size, u32 alignment);
		iavf_status i40e_free_dma_mem(struct iavf_hw hw, struct i40e_dma_mem mem);
		iavf_status i40e_allocate_virt_mem(struct iavf_hw *hw,
		struct i40e_virt_mem *mem, u32 size);
		iavf_status i40e_free_virt_mem(struct iavf_hw hw, struct i40e_virt_mem mem);
		iavf_status iavf_free_dma_mem(struct iavf_hw hw, struct iavf_dma_mem mem);
		iavf_status iavf_allocate_virt_mem(struct iavf_hw *hw,
		struct iavf_virt_mem *mem, u32 size);
		iavf_status iavf_free_virt_mem(struct iavf_hw hw, struct iavf_virt_mem mem);

		#endif /* _I40E_ALLOC_H_ */
		#endif /* _IAVF_ALLOC_H_ */

drivers/net/ethernet/intel/iavf/i40e_common.c

+295 −295

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