Unverified Commit 55de0f31 authored by Jernej Skrabec's avatar Jernej Skrabec Committed by Maxime Ripard
Browse files

clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO 



CLK_PLL_VIDEO needs to be referenced in HDMI DT entry as a possible
PHY clock parent.

Export it so it can be used later in DT.

Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
parent b1a1ad4b

drivers/clk/sunxi-ng/ccu-sun8i-h3.h

+3 −1
Original line number Diff line number Diff line
@@ -26,7 +26,9 @@ 
#define CLK_PLL_AUDIO_2X	3

#define CLK_PLL_AUDIO_4X	4

#define CLK_PLL_AUDIO_8X	5

#define CLK_PLL_VIDEO		6



/* PLL_VIDEO is exported */



#define CLK_PLL_VE		7

#define CLK_PLL_DDR		8

include/dt-bindings/clock/sun8i-h3-ccu.h

+2 −0
Original line number Diff line number Diff line
@@ -43,6 +43,8 @@ 
#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_

#define _DT_BINDINGS_CLK_SUN8I_H3_H_



#define CLK_PLL_VIDEO		6



#define CLK_PLL_PERIPH0		9



#define CLK_CPUX		14

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