Commit 55db8ac6 authored by Takeshi Kihara's avatar Takeshi Kihara Committed by Simon Horman
Browse files

arm64: dts: renesas: r8a77965: Add CAN and CANFD controller nodes 



This patch adds CAN{0,1} and CANFD controller nodes for the R8A77965 SoC.

Signed-off-by: default avatarTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: default avatarMarek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent ba3ac35b

arch/arm64/boot/dts/renesas/r8a77965.dtsi

+49 −2
Original line number Diff line number Diff line
@@ -907,13 +907,60 @@ 
		};



		can0: can@e6c30000 {

			compatible = "renesas,can-r8a77965",

				     "renesas,rcar-gen3-can";

			reg = <0 0xe6c30000 0 0x1000>;

			/* placeholder */

			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 916>,

			       <&cpg CPG_CORE R8A77965_CLK_CANFD>,

			       <&can_clk>;

			clock-names = "clkp1", "clkp2", "can_clk";

			assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;

			assigned-clock-rates = <40000000>;

			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;

			resets = <&cpg 916>;

			status = "disabled";

		};



		can1: can@e6c38000 {

			compatible = "renesas,can-r8a77965",

				     "renesas,rcar-gen3-can";

			reg = <0 0xe6c38000 0 0x1000>;

			/* placeholder */

			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 915>,

			       <&cpg CPG_CORE R8A77965_CLK_CANFD>,

			       <&can_clk>;

			clock-names = "clkp1", "clkp2", "can_clk";

			assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;

			assigned-clock-rates = <40000000>;

			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;

			resets = <&cpg 915>;

			status = "disabled";

		};



		canfd: can@e66c0000 {

			compatible = "renesas,r8a77965-canfd",

				     "renesas,rcar-gen3-canfd";

			reg = <0 0xe66c0000 0 0x8000>;

			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,

				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 914>,

			       <&cpg CPG_CORE R8A77965_CLK_CANFD>,

			       <&can_clk>;

			clock-names = "fck", "canfd", "can_clk";

			assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;

			assigned-clock-rates = <40000000>;

			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;

			resets = <&cpg 914>;

			status = "disabled";



			channel0 {

				status = "disabled";

			};



			channel1 {

				status = "disabled";

			};

		};



		pwm0: pwm@e6e30000 {

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