Merge tag 'for-5.11-clk' of... (55cd03e8) · Commits · 戴 / test

drivers/clk/tegra/clk-bpmp.c

+3 −3

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (C) 2016 NVIDIA Corporation
		* Copyright (C) 2016-2020 NVIDIA Corporation
		*/

		#include <linux/clk-provider.h>
		@@ -174,7 +174,7 @@ static long tegra_bpmp_clk_round_rate(struct clk_hw *hw, unsigned long rate,
		int err;

		memset(&request, 0, sizeof(request));
		request.rate = rate;
		request.rate = min_t(u64, rate, S64_MAX);

		memset(&msg, 0, sizeof(msg));
		msg.cmd = CMD_CLK_ROUND_RATE;
		@@ -256,7 +256,7 @@ static int tegra_bpmp_clk_set_rate(struct clk_hw *hw, unsigned long rate,
		struct tegra_bpmp_clk_message msg;

		memset(&request, 0, sizeof(request));
		request.rate = rate;
		request.rate = min_t(u64, rate, S64_MAX);

		memset(&msg, 0, sizeof(msg));
		msg.cmd = CMD_CLK_SET_RATE;

+2 −2

Original line number	Diff line number	Diff line
		@@ -1856,13 +1856,13 @@ static int dfll_fetch_pwm_params(struct tegra_dfll *td)
		&td->reg_init_uV);
		if (!ret) {
		dev_err(td->dev, "couldn't get initialized voltage\n");
		return ret;
		return -EINVAL;
		}

		ret = read_dt_param(td, "nvidia,pwm-period-nanoseconds", &pwm_period);
		if (!ret) {
		dev_err(td->dev, "couldn't get PWM period\n");
		return ret;
		return -EINVAL;
		}
		td->pwm_rate = (NSEC_PER_SEC / pwm_period) * (MAX_DFLL_VOLTAGES - 1);