mlxsw: reg: Add Management UTC Register (55a8b001) · Commits · 戴 / test

drivers/net/ethernet/mellanox/mlxsw/reg.h

+45 −0

Original line number	Diff line number	Diff line
		@@ -8691,6 +8691,50 @@ static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
		MLXSW_REG_MLCR_DURATION_MAX : 0);
		}

		/* MTUTC - Management UTC Register
		* -------------------------------
		* Configures the HW UTC counter.
		*/
		#define MLXSW_REG_MTUTC_ID 0x9055
		#define MLXSW_REG_MTUTC_LEN 0x1C

		MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN);

		enum mlxsw_reg_mtutc_operation {
		MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0,
		MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3,
		};

		/* reg_mtutc_operation
		* Operation.
		* Access: OP
		*/
		MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4);

		/* reg_mtutc_freq_adjustment
		* Frequency adjustment: Every PPS the HW frequency will be
		* adjusted by this value. Units of HW clock, where HW counts
		* 10^9 HW clocks for 1 HW second.
		* Access: RW
		*/
		MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32);

		/* reg_mtutc_utc_sec
		* UTC seconds.
		* Access: WO
		*/
		MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32);

		static inline void
		mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper,
		u32 freq_adj, u32 utc_sec)
		{
		MLXSW_REG_ZERO(mtutc, payload);
		mlxsw_reg_mtutc_operation_set(payload, oper);
		mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj);
		mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec);
		}

		/* MCQI - Management Component Query Information
		* ---------------------------------------------
		* This register allows querying information about firmware components.
		@@ -10105,6 +10149,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
		MLXSW_REG(mgir),
		MLXSW_REG(mrsr),
		MLXSW_REG(mlcr),
		MLXSW_REG(mtutc),
		MLXSW_REG(mpsc),
		MLXSW_REG(mcqi),
		MLXSW_REG(mcc),

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