Commit 55a7d4b8 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-4.2' of git://git.sourceforge.jp/gitroot/uclinux-h8/linux 

Pull Renesas H8/300 architecture re-introduction from Yoshinori Sato.

We dropped arch/h8300 two years ago as stale and old, this is a new and
more modern rewritten arch support for the same architecture.

* tag 'for-4.2' of git://git.sourceforge.jp/gitroot/uclinux-h8/linux: (27 commits)
  h8300: fix typo.
  h8300: Always build dtb
  h8300: Remove ARCH_WANT_IPC_PARSE_VERSION
  sh-sci: Get register size from platform device
  clk: h8300: fix error handling in h8s2678_pll_clk_setup()
  h8300: Symbol name fix
  h8300: devicetree source
  h8300: configs
  h8300: IRQ chip driver
  h8300: clocksource
  h8300: clock driver
  h8300: Build scripts
  h8300: library functions
  h8300: Memory management
  h8300: miscellaneous functions
  h8300: process helpers
  h8300: compressed image support
  h8300: Low level entry
  h8300: kernel startup
  h8300: Interrupt and exceptions
  ...
parents aefbef10 07834743

CREDITS

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Original line number Diff line number Diff line
@@ -3219,11 +3219,6 @@ N: Dipankar Sarma 
E: dipankar@in.ibm.com

D: RCU



N: Yoshinori Sato

E: ysato@users.sourceforge.jp

D: uClinux for Renesas H8/300 (H8300)

D: http://uclinux-h8.sourceforge.jp/



N: Hannu Savolainen

E: hannu@opensound.com

D: Maintainer of the sound drivers until 2.1.x days.

Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt

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* Renesas H8/300 divider clock



Required Properties:



  - compatible: Must be "renesas,sh73a0-h8300-div-clock"



  - clocks: Reference to the parent clocks ("extal1" and "extal2")



  - #clock-cells: Must be 1



  - reg: Base address and length of the divide rate selector



  - renesas,width: bit width of selector



Example

-------



		cclk: cclk {

			compatible = "renesas,h8300-div-clock";

			clocks = <&xclk>;

			#clock-cells = <0>;

			reg = <0xfee01b 2>;

			renesas,width = <2>;

		};

Documentation/devicetree/bindings/clock/renesas,h8s2678-pll-clock.txt

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Renesas H8S2678 PLL clock



This device is Clock multiplyer



Required Properties:



  - compatible: Must be "renesas,h8s2678-pll-clock"



  - clocks: Reference to the parent clocks



  - #clock-cells: Must be 0



  - reg: Two rate selector (Multiply / Divide) register address



Example

-------



		pllclk: pllclk {

			compatible = "renesas,h8s2678-pll-clock";

			clocks = <&xclk>;

			#clock-cells = <0>;

			reg = <0xfee03b 2>, <0xfee045 2>;

		};

Documentation/devicetree/bindings/h8300/cpu.txt

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* H8/300 CPU bindings



Required properties:



- compatible: Compatible property value should be "renesas,h8300".

- clock-frequency: Contains the clock frequency for CPU, in Hz.



Example:



		cpu@0 {

			compatible = "renesas,h8300";

			clock-frequency = <20000000>;

		};

Documentation/devicetree/bindings/interrupt-controller/renesas,h8300h-intc.txt

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* H8/300H Interrupt controller



Required properties:



- compatible: has to be "renesas,h8300h-intc", "renesas,h8300-intc" as fallback.

- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in

  interrupts.txt in this directory

- regs: Base address of interrupt controller registers.



Optional properties:



- any properties, listed in interrupts.txt, and any standard resource allocation

  properties



Example:



	h8intc: interrupt-controller@fee012 {

		compatible = "renesas,h8300h-intc", "renesas,h8300-intc";

		#interrupt-cells = <2>;

		interrupt-controller;

		reg = <0xfee012 7>;

	};

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