drivers: base: cacheinfo: fix boot error message when acpi is enabled (55877ef4) · Commits · 戴 / test

ARM64 enables both CONFIG_OF and CONFIG_ACPI and the firmware can pass both ACPI tables and the device tree. Based on the kernel parameter, one of the two will be chosen. If acpi is enabled, then device tree is not unflattened. Currently ARM64 platforms report: " Failed to find cpu0 device node Unable to detect cache hierarchy from DT for CPU 0 " which is incorrect when booting with ACPI. Also latest ACPI v6.1 has no support for cache properties/hierarchy. This patch adds check for unflattened device tree and also returns as "not supported" if ACPI is runtime enabled. It also removes the reference to DT from the error message as the cache hierarchy can be detected from the firmware(OF/DT/ACPI) Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by:

Sudeep Holla <sudeep.holla@arm.com> Signed-off-by:

Greg Kroah-Hartman <gregkh@linuxfoundation.org>

drivers/base/cacheinfo.c

+8 −4

Original line number	Diff line number	Diff line
		@@ -16,6 +16,7 @@
		* You should have received a copy of the GNU General Public License
		* along with this program. If not, see <http://www.gnu.org/licenses/>.
		*/
		#include <linux/acpi.h>
		#include <linux/bitops.h>
		#include <linux/cacheinfo.h>
		#include <linux/compiler.h>
		@@ -104,12 +105,16 @@ static int cache_shared_cpu_map_setup(unsigned int cpu)
		struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
		struct cacheinfo this_leaf, sib_leaf;
		unsigned int index;
		int ret;
		int ret = 0;

		if (this_cpu_ci->cpu_map_populated)
		return 0;

		if (of_have_populated_dt())
		ret = cache_setup_of_node(cpu);
		else if (!acpi_disabled)
		/* No cache property/hierarchy support yet in ACPI */
		ret = -ENOTSUPP;
		if (ret)
		return ret;

		@@ -206,8 +211,7 @@ static int detect_cache_attributes(unsigned int cpu)
		*/
		ret = cache_shared_cpu_map_setup(cpu);
		if (ret) {
		pr_warn("Unable to detect cache hierarchy from DT for CPU %d\n",
		cpu);
		pr_warn("Unable to detect cache hierarchy for CPU %d\n", cpu);
		goto free_ci;
		}
		return 0;

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