clk: socfpga: Fix integer overflow in clock calculation (5585f731) · Commits · 戴 / test

Use 64-bit integer for calculating clock rate. Also use do_div for the 64-bit division. Signed-off-by:

Dinh Nguyen <dinguyen@altera.com> Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by:

drivers/clk/socfpga/clk-pll.c

+5 −3

Original line number	Diff line number	Diff line
		@@ -44,7 +44,8 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
		unsigned long parent_rate)
		{
		struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
		unsigned long divf, divq, vco_freq, reg;
		unsigned long divf, divq, reg;
		unsigned long long vco_freq;
		unsigned long bypass;

		reg = readl(socfpgaclk->hw.reg);
		@@ -54,8 +55,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,

		divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
		divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
		vco_freq = parent_rate * (divf + 1);
		return vco_freq / (1 + divq);
		vco_freq = (unsigned long long)parent_rate * (divf + 1);
		do_div(vco_freq, (1 + divq));
		return (unsigned long)vco_freq;
		}

		static struct clk_ops clk_pll_ops = {