mmc: mediatek: refine msdc timeout api (557011b6) · Commits · 戴 / test

drivers/mmc/host/mtk-sd.c

+22 −10

Original line number	Diff line number	Diff line
		@@ -723,21 +723,21 @@ static void msdc_unprepare_data(struct msdc_host host, struct mmc_request mrq)
		}
		}

		/* clock control primitives */
		static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
		static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
		{
		u32 timeout, clk_ns;
		u64 timeout, clk_ns;
		u32 mode = 0;

		host->timeout_ns = ns;
		host->timeout_clks = clks;
		if (host->mmc->actual_clock == 0) {
		timeout = 0;
		} else {
		clk_ns = 1000000000UL / host->mmc->actual_clock;
		timeout = (ns + clk_ns - 1) / clk_ns + clks;
		clk_ns = 1000000000ULL;
		do_div(clk_ns, host->mmc->actual_clock);
		timeout = ns + clk_ns - 1;
		do_div(timeout, clk_ns);
		timeout += clks;
		/* in 1048576 sclk cycle unit */
		timeout = (timeout + (0x1 << 20) - 1) >> 20;
		timeout = DIV_ROUND_UP(timeout, (0x1 << 20));
		if (host->dev_comp->clk_div_bits == 8)
		sdr_get_field(host->base + MSDC_CFG,
		MSDC_CFG_CKMOD, &mode);
		@@ -747,9 +747,21 @@ static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
		/DDR mode will double the clk cycles for data timeout /
		timeout = mode >= 2 ? timeout * 2 : timeout;
		timeout = timeout > 1 ? timeout - 1 : 0;
		timeout = timeout > 255 ? 255 : timeout;
		}
		sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout);
		return timeout;
		}

		/* clock control primitives */
		static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
		{
		u64 timeout;

		host->timeout_ns = ns;
		host->timeout_clks = clks;

		timeout = msdc_timeout_cal(host, ns, clks);
		sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
		(u32)(timeout > 255 ? 255 : timeout));
		}

		static void msdc_gate_clock(struct msdc_host *host)

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