Commit 555e2a5c authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'sirf-soc-for-3.15' of... 

Merge tag 'sirf-soc-for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux into next/cleanup

ARM: sirf: machine update for 3.15 from Barry Song:

Most of the below are some minor fixes for coding style. "ARM: prima2:
move to generic reset controller driver framework" has been ready near
3.14 merge window, but it was late to merge in 3.14, so move this one
to 3.15.

* tag 'sirf-soc-for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux

:
  ARM: prima2: move to generic reset controller driver framework
  ARM: prima2: staticize sirfsoc_init_late function
  ARM: prima2: rtciobrg: fix the typo about license
  ARM: prima2: common: fix checkpatch issues
  ARM: prima2: platsmp: fix checkpatch issues
  ARM: prima2: l2x0: fix checkpatch issues

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents dba5bedb e7eda91f

Documentation/devicetree/bindings/reset/sirf,rstc.txt

0 → 100644
+42 −0
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CSR SiRFSoC Reset Controller

======================================



Please also refer to reset.txt in this directory for common reset

controller binding usage.



Required properties:

- compatible: Should be "sirf,prima2-rstc" or "sirf,marco-rstc"

- reg: should be register base and length as documented in the

  datasheet

- #reset-cells: 1, see below



example:



rstc: reset-controller@88010000 {

	compatible = "sirf,prima2-rstc";

	reg = <0x88010000 0x1000>;

	#reset-cells = <1>;

};



Specifying reset lines connected to IP modules

==============================================



The reset controller(rstc) manages various reset sources. This module provides

reset signals for most blocks in system. Those device nodes should specify the

reset line on the rstc in their resets property, containing a phandle to the

rstc device node and a RESET_INDEX specifying which module to reset, as described

in reset.txt.



For SiRFSoC, RESET_INDEX is just reset_bit defined in SW_RST0 and SW_RST1 registers.

For modules whose rest_bit is in SW_RST0, its RESET_INDEX is 0~31. For modules whose

rest_bit is in SW_RST1, its RESET_INDEX is 32~63.



example:



vpp@90020000 {

	compatible = "sirf,prima2-vpp";

	reg = <0x90020000 0x10000>;

	interrupts = <31>;

	clocks = <&clks 35>;

	resets = <&rstc 6>;

};

arch/arm/boot/dts/atlas6.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -65,9 +65,10 @@ 
				#clock-cells = <1>;

			};



			reset-controller@88010000 {

			rstc: reset-controller@88010000 {

				compatible = "sirf,prima2-rstc";

				reg = <0x88010000 0x1000>;

				#reset-cells = <1>;

			};



			rsc-controller@88020000 {

arch/arm/boot/dts/marco.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -58,9 +58,10 @@ 
			#size-cells = <1>;

			ranges = <0xc2000000 0xc2000000 0x1000000>;



			reset-controller@c2000000 {

			rstc: reset-controller@c2000000 {

				compatible = "sirf,marco-rstc";

				reg = <0xc2000000 0x10000>;

				#reset-cells = <1>;

			};

		};

arch/arm/boot/dts/prima2.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -76,9 +76,10 @@ 
				#clock-cells = <1>;

			};



			reset-controller@88010000 {

			rstc: reset-controller@88010000 {

				compatible = "sirf,prima2-rstc";

				reg = <0x88010000 0x1000>;

				#reset-cells = <1>;

			};



			rsc-controller@88020000 {

arch/arm/mach-prima2/Kconfig

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Original line number Diff line number Diff line 
config ARCH_SIRF

	bool "CSR SiRF" if ARCH_MULTI_V7

	select ARCH_HAS_RESET_CONTROLLER

	select ARCH_REQUIRE_GPIOLIB

	select GENERIC_IRQ_CHIP

	select NO_IOPORT

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