Commit 552ae76f authored by Marc Zyngier's avatar Marc Zyngier
Browse files

arm64: Detect the ARMv8.4 TTL feature 



In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL
feature allows TLBs to be issued with a level allowing for quicker
invalidation.

Let's detect the feature for now. Further patches will implement
its actual usage.

Reviewed-by : Suzuki K Polose <suzuki.poulose@arm.com>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent 9ebcfadb

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -62,7 +62,8 @@ 
#define ARM64_HAS_GENERIC_AUTH			52

#define ARM64_HAS_32BIT_EL1			53

#define ARM64_BTI				54

#define ARM64_HAS_ARMv8_4_TTL			55



#define ARM64_NCAPS				55

#define ARM64_NCAPS				56



#endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/sysreg.h

+1 −0
Original line number Diff line number Diff line
@@ -746,6 +746,7 @@ 


/* id_aa64mmfr2 */

#define ID_AA64MMFR2_E0PD_SHIFT		60

#define ID_AA64MMFR2_TTL_SHIFT		48

#define ID_AA64MMFR2_FWB_SHIFT		40

#define ID_AA64MMFR2_AT_SHIFT		32

#define ID_AA64MMFR2_LVA_SHIFT		16

arch/arm64/kernel/cpufeature.c

+11 −0
Original line number Diff line number Diff line
@@ -323,6 +323,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 


static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
@@ -1882,6 +1883,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.matches = has_cpuid_feature,

		.cpu_enable = cpu_has_fwb,

	},

	{

		.desc = "ARMv8.4 Translation Table Level",

		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.capability = ARM64_HAS_ARMv8_4_TTL,

		.sys_reg = SYS_ID_AA64MMFR2_EL1,

		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64MMFR2_TTL_SHIFT,

		.min_field_value = 1,

		.matches = has_cpuid_feature,

	},

#ifdef CONFIG_ARM64_HW_AFDBM

	{

		/*

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