Commit 54eda9df authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pci-v4.19-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci 

Pull PCI fixes from Bjorn Helgaas:

 - Add Tyrel Datwyler as maintainer for PPC64 RPA hotplug (Tyrel
   Datwyler)

 - Add Gustavo Pimentel as DesignWare PCI maintainer (Joao Pinto)

 - Fix a Switchtec Spectre v1 vulnerability (Gustavo A. R. Silva)

 - Revert an unnecessary Intel 300 ACS quirk (Mika Westerberg)

 - Fix pciehp hot-add/powerfault detection that left indicators in wrong
   state (Keith Busch)

 - Fix pci_reset_bus() logic error (Dennis Dalessandro)

 - Revert IB/hfi1 PCI reset change that caused a deadlock (Dennis
   Dalessandro)

 - Allow enabling PASID on Root Complex Integrated Endpoints (Felix
   Kuehling)

* tag 'pci-v4.19-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  PCI: Fix enabling of PASID on RC integrated endpoints
  IB/hfi1,PCI: Allow bus reset while probing
  PCI: Fix faulty logic in pci_reset_bus()
  PCI: pciehp: Fix hot-add vs powerfault detection order
  switchtec: Fix Spectre v1 vulnerability
  Revert "PCI: Add ACS quirk for Intel 300 series"
  MAINTAINERS: Add Gustavo Pimentel as DesignWare PCI maintainer
  MAINTAINERS: Add entries for PPC64 RPA PCI hotplug drivers
parents d3bd5973 9d27e39d

MAINTAINERS

+15 −1
Original line number Diff line number Diff line
@@ -7016,6 +7016,20 @@ F: drivers/crypto/vmx/aes* 
F:	drivers/crypto/vmx/ghash*

F:	drivers/crypto/vmx/ppc-xlate.pl



IBM Power PCI Hotplug Driver for RPA-compliant PPC64 platform

M:	Tyrel Datwyler <tyreld@linux.vnet.ibm.com>

L:	linux-pci@vger.kernel.org

L:	linuxppc-dev@lists.ozlabs.org

S:	Supported

F:	drivers/pci/hotplug/rpaphp*



IBM Power IO DLPAR Driver for RPA-compliant PPC64 platform

M:	Tyrel Datwyler <tyreld@linux.vnet.ibm.com>

L:	linux-pci@vger.kernel.org

L:	linuxppc-dev@lists.ozlabs.org

S:	Supported

F:	drivers/pci/hotplug/rpadlpar*



IBM ServeRAID RAID DRIVER

S:	Orphan

F:	drivers/scsi/ips.*
@@ -11154,7 +11168,7 @@ F: drivers/pci/controller/dwc/pci-exynos.c 


PCI DRIVER FOR SYNOPSYS DESIGNWARE

M:	Jingoo Han <jingoohan1@gmail.com>

M:	Joao Pinto <Joao.Pinto@synopsys.com>

M:	Gustavo Pimentel <gustavo.pimentel@synopsys.com>

L:	linux-pci@vger.kernel.org

S:	Maintained

F:	Documentation/devicetree/bindings/pci/designware-pcie.txt

drivers/infiniband/hw/hfi1/pcie.c

+4 −7
Original line number Diff line number Diff line
@@ -893,14 +893,11 @@ static int trigger_sbr(struct hfi1_devdata *dd) 
		}



	/*

	 * A secondary bus reset (SBR) issues a hot reset to our device.

	 * The following routine does a 1s wait after the reset is dropped

	 * per PCI Trhfa (recovery time).  PCIe 3.0 section 6.6.1 -

	 * Conventional Reset, paragraph 3, line 35 also says that a 1s

	 * delay after a reset is required.  Per spec requirements,

	 * the link is either working or not after that point.

	 * This is an end around to do an SBR during probe time. A new API needs

	 * to be implemented to have cleaner interface but this fixes the

	 * current brokenness

	 */

	return pci_reset_bus(dev);

	return pci_bridge_secondary_bus_reset(dev->bus->self);

}



/*

drivers/pci/hotplug/pciehp_hpc.c

+9 −9
Original line number Diff line number Diff line
@@ -496,7 +496,7 @@ int pciehp_power_on_slot(struct slot *slot) 
	u16 slot_status;

	int retval;



	/* Clear sticky power-fault bit from previous power failures */

	/* Clear power-fault bit from previous power failures */

	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);

	if (slot_status & PCI_EXP_SLTSTA_PFD)

		pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
@@ -646,6 +646,14 @@ static irqreturn_t pciehp_ist(int irq, void *dev_id) 
		pciehp_handle_button_press(slot);

	}



	/* Check Power Fault Detected */

	if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {

		ctrl->power_fault_detected = 1;

		ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(slot));

		pciehp_set_attention_status(slot, 1);

		pciehp_green_led_off(slot);

	}



	/*

	 * Disable requests have higher priority than Presence Detect Changed

	 * or Data Link Layer State Changed events.
@@ -657,14 +665,6 @@ static irqreturn_t pciehp_ist(int irq, void *dev_id) 
		pciehp_handle_presence_or_link_change(slot, events);

	up_read(&ctrl->reset_lock);



	/* Check Power Fault Detected */

	if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {

		ctrl->power_fault_detected = 1;

		ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(slot));

		pciehp_set_attention_status(slot, 1);

		pciehp_green_led_off(slot);

	}



	pci_config_pm_runtime_put(pdev);

	wake_up(&ctrl->requester);

	return IRQ_HANDLED;

drivers/pci/pci.c

+2 −1
Original line number Diff line number Diff line
@@ -4547,6 +4547,7 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev) 


	return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);

}

EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);



static int pci_parent_bus_reset(struct pci_dev *dev, int probe)

{
@@ -5200,7 +5201,7 @@ static int __pci_reset_bus(struct pci_bus *bus) 
 */

int pci_reset_bus(struct pci_dev *pdev)

{

	return pci_probe_reset_slot(pdev->slot) ?

	return (!pci_probe_reset_slot(pdev->slot)) ?

	    __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);

}

EXPORT_SYMBOL_GPL(pci_reset_bus);

drivers/pci/probe.c

+4 −1
Original line number Diff line number Diff line
@@ -2074,6 +2074,7 @@ static void pci_configure_eetlp_prefix(struct pci_dev *dev) 
{

#ifdef CONFIG_PCI_PASID

	struct pci_dev *bridge;

	int pcie_type;

	u32 cap;



	if (!pci_is_pcie(dev))
@@ -2083,7 +2084,9 @@ static void pci_configure_eetlp_prefix(struct pci_dev *dev) 
	if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))

		return;



	if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)

	pcie_type = pci_pcie_type(dev);

	if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||

	    pcie_type == PCI_EXP_TYPE_RC_END)

		dev->eetlp_prefix_path = 1;

	else {

		bridge = pci_upstream_bridge(dev);

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