Commit 54d792f2 authored by Andrew Lunn's avatar Andrew Lunn Committed by David S. Miller
Browse files

net: dsa: Centralise global and port setup code into mv88e6xxx. 



The port setup code in the individual drivers is identical for 6123,
6171, and 6352, and very similar in 6131. Move it all into mv88e6xxx,
using the chip families to differentiate on features.

Similarly, the global setup is also very similar. Move the majority
into mv8e6xxx.

The chips themselves fall into families. Add helpers which uses the
device IDs to determine if a device is a member of a family or not.
Add some additional device IDs to the existing list, to make these
helper functions more complete. However these IDs are not yet added to
the probe functions.

Signed-off-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 239fb791

drivers/net/dsa/mv88e6123_61_65.c

+5 −163
Original line number Diff line number Diff line
@@ -55,7 +55,10 @@ static char *mv88e6123_61_65_probe(struct device *host_dev, int sw_addr) 
static int mv88e6123_61_65_setup_global(struct dsa_switch *ds)

{

	int ret;

	int i;



	ret = mv88e6xxx_setup_global(ds);

	if (ret)

		return ret;



	/* Disable the PHY polling unit (since there won't be any

	 * external PHYs to poll), don't discard packets with
@@ -63,17 +66,6 @@ static int mv88e6123_61_65_setup_global(struct dsa_switch *ds) 
	 */

	REG_WRITE(REG_GLOBAL, 0x04, 0x0000);



	/* Set the default address aging time to 5 minutes, and

	 * enable address learn messages to be sent to all message

	 * ports.

	 */

	REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);



	/* Configure the priority mapping registers. */

	ret = mv88e6xxx_config_prio(ds);

	if (ret < 0)

		return ret;



	/* Configure the upstream port, and configure the upstream

	 * port as the port to which ingress and egress monitor frames

	 * are to be sent.
@@ -85,157 +77,9 @@ static int mv88e6123_61_65_setup_global(struct dsa_switch *ds) 
	 */

	REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);



	/* Send all frames with destination addresses matching

	 * 01:80:c2:00:00:2x to the CPU port.

	 */

	REG_WRITE(REG_GLOBAL2, 0x02, 0xffff);



	/* Send all frames with destination addresses matching

	 * 01:80:c2:00:00:0x to the CPU port.

	 */

	REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);



	/* Disable the loopback filter, disable flow control

	 * messages, disable flood broadcast override, disable

	 * removing of provider tags, disable ATU age violation

	 * interrupts, disable tag flow control, force flow

	 * control priority to the highest, and send all special

	 * multicast frames to the CPU at the highest priority.

	 */

	REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);



	/* Program the DSA routing table. */

	for (i = 0; i < 32; i++) {

		int nexthop;



		nexthop = 0x1f;

		if (i != ds->index && i < ds->dst->pd->nr_chips)

			nexthop = ds->pd->rtable[i] & 0x1f;



		REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);

	}



	/* Clear all trunk masks. */

	for (i = 0; i < 8; i++)

		REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0xff);



	/* Clear all trunk mappings. */

	for (i = 0; i < 16; i++)

		REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));



	/* Disable ingress rate limiting by resetting all ingress

	 * rate limit registers to their initial state.

	 */

	for (i = 0; i < 6; i++)

		REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8));



	/* Initialise cross-chip port VLAN table to reset defaults. */

	REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000);



	/* Clear the priority override table. */

	for (i = 0; i < 16; i++)

		REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8));



	/* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */



	return 0;

}



static int mv88e6123_61_65_setup_port(struct dsa_switch *ds, int p)

{

	int addr = REG_PORT(p);

	u16 val;



	/* MAC Forcing register: don't force link, speed, duplex

	 * or flow control state to any particular values on physical

	 * ports, but force the CPU port and all DSA ports to 1000 Mb/s

	 * full duplex.

	 */

	if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))

		REG_WRITE(addr, 0x01, 0x003e);

	else

		REG_WRITE(addr, 0x01, 0x0003);



	/* Do not limit the period of time that this port can be

	 * paused for by the remote end or the period of time that

	 * this port can pause the remote end.

	 */

	REG_WRITE(addr, 0x02, 0x0000);



	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,

	 * disable Header mode, enable IGMP/MLD snooping, disable VLAN

	 * tunneling, determine priority by looking at 802.1p and IP

	 * priority fields (IP prio has precedence), and set STP state

	 * to Forwarding.

	 *

	 * If this is the CPU link, use DSA or EDSA tagging depending

	 * on which tagging mode was configured.

	 *

	 * If this is a link to another switch, use DSA tagging mode.

	 *

	 * If this is the upstream port for this switch, enable

	 * forwarding of unknown unicasts and multicasts.

	 */

	val = 0x0433;

	if (dsa_is_cpu_port(ds, p)) {

		if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)

			val |= 0x3300;

		else

			val |= 0x0100;

	}

	if (ds->dsa_port_mask & (1 << p))

		val |= 0x0100;

	if (p == dsa_upstream_port(ds))

		val |= 0x000c;

	REG_WRITE(addr, 0x04, val);



	/* Port Control 2: don't force a good FCS, set the maximum

	 * frame size to 10240 bytes, don't let the switch add or

	 * strip 802.1q tags, don't discard tagged or untagged frames

	 * on this port, do a destination address lookup on all

	 * received packets as usual, disable ARP mirroring and don't

	 * send a copy of all transmitted/received frames on this port

	 * to the CPU.

	 */

	REG_WRITE(addr, 0x08, 0x2080);



	/* Egress rate control: disable egress rate control. */

	REG_WRITE(addr, 0x09, 0x0001);



	/* Egress rate control 2: disable egress rate control. */

	REG_WRITE(addr, 0x0a, 0x0000);



	/* Port Association Vector: when learning source addresses

	 * of packets, add the address to the address database using

	 * a port bitmap that has only the bit for this port set and

	 * the other bits clear.

	 */

	REG_WRITE(addr, 0x0b, 1 << p);



	/* Port ATU control: disable limiting the number of address

	 * database entries that this port is allowed to use.

	 */

	REG_WRITE(addr, 0x0c, 0x0000);



	/* Priority Override: disable DA, SA and VTU priority override. */

	REG_WRITE(addr, 0x0d, 0x0000);



	/* Port Ethertype: use the Ethertype DSA Ethertype value. */

	REG_WRITE(addr, 0x0f, ETH_P_EDSA);



	/* Tag Remap: use an identity 802.1p prio -> switch prio

	 * mapping.

	 */

	REG_WRITE(addr, 0x18, 0x3210);



	/* Tag Remap 2: use an identity 802.1p prio -> switch prio

	 * mapping.

	 */

	REG_WRITE(addr, 0x19, 0x7654);



	return mv88e6xxx_setup_port_common(ds, p);

}



static int mv88e6123_61_65_setup(struct dsa_switch *ds)

{

	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
@@ -262,14 +106,12 @@ static int mv88e6123_61_65_setup(struct dsa_switch *ds) 
	if (ret < 0)

		return ret;



	/* @@@ initialise vtu and atu */



	ret = mv88e6123_61_65_setup_global(ds);

	if (ret < 0)

		return ret;



	for (i = 0; i < ps->num_ports; i++) {

		ret = mv88e6123_61_65_setup_port(ds, i);

		ret = mv88e6xxx_setup_port(ds, i);

		if (ret < 0)

			return ret;

	}

drivers/net/dsa/mv88e6131.c

+5 −144
Original line number Diff line number Diff line
@@ -45,7 +45,10 @@ static char *mv88e6131_probe(struct device *host_dev, int sw_addr) 
static int mv88e6131_setup_global(struct dsa_switch *ds)

{

	int ret;

	int i;



	ret = mv88e6xxx_setup_global(ds);

	if (ret)

		return ret;



	/* Enable the PHY polling unit, don't discard packets with

	 * excessive collisions, use a weighted fair queueing scheme
@@ -54,17 +57,6 @@ static int mv88e6131_setup_global(struct dsa_switch *ds) 
	 */

	REG_WRITE(REG_GLOBAL, 0x04, 0x4400);



	/* Set the default address aging time to 5 minutes, and

	 * enable address learn messages to be sent to all message

	 * ports.

	 */

	REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);



	/* Configure the priority mapping registers. */

	ret = mv88e6xxx_config_prio(ds);

	if (ret < 0)

		return ret;



	/* Set the VLAN ethertype to 0x8100. */

	REG_WRITE(REG_GLOBAL, 0x19, 0x8100);
@@ -83,38 +75,6 @@ static int mv88e6131_setup_global(struct dsa_switch *ds) 
	else

		REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 | (ds->index & 0x1f));



	/* Send all frames with destination addresses matching

	 * 01:80:c2:00:00:0x to the CPU port.

	 */

	REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);



	/* Ignore removed tag data on doubly tagged packets, disable

	 * flow control messages, force flow control priority to the

	 * highest, and send all special multicast frames to the CPU

	 * port at the highest priority.

	 */

	REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);



	/* Program the DSA routing table. */

	for (i = 0; i < 32; i++) {

		int nexthop;



		nexthop = 0x1f;

		if (ds->pd->rtable &&

		    i != ds->index && i < ds->dst->pd->nr_chips)

			nexthop = ds->pd->rtable[i] & 0x1f;



		REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);

	}



	/* Clear all trunk masks. */

	for (i = 0; i < 8; i++)

		REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7ff);



	/* Clear all trunk mappings. */

	for (i = 0; i < 16; i++)

		REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));



	/* Force the priority of IGMP/MLD snoop frames and ARP frames

	 * to the highest setting.

	 */
@@ -123,103 +83,6 @@ static int mv88e6131_setup_global(struct dsa_switch *ds) 
	return 0;

}



static int mv88e6131_setup_port(struct dsa_switch *ds, int p)

{

	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);

	int addr = REG_PORT(p);

	u16 val;



	/* MAC Forcing register: don't force link, speed, duplex

	 * or flow control state to any particular values on physical

	 * ports, but force the CPU port and all DSA ports to 1000 Mb/s

	 * (100 Mb/s on 6085) full duplex.

	 */

	if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))

		if (ps->id == PORT_SWITCH_ID_6085)

			REG_WRITE(addr, 0x01, 0x003d); /* 100 Mb/s */

		else

			REG_WRITE(addr, 0x01, 0x003e); /* 1000 Mb/s */

	else

		REG_WRITE(addr, 0x01, 0x0003);



	/* Port Control: disable Core Tag, disable Drop-on-Lock,

	 * transmit frames unmodified, disable Header mode,

	 * enable IGMP/MLD snoop, disable DoubleTag, disable VLAN

	 * tunneling, determine priority by looking at 802.1p and

	 * IP priority fields (IP prio has precedence), and set STP

	 * state to Forwarding.

	 *

	 * If this is the upstream port for this switch, enable

	 * forwarding of unknown unicasts, and enable DSA tagging

	 * mode.

	 *

	 * If this is the link to another switch, use DSA tagging

	 * mode, but do not enable forwarding of unknown unicasts.

	 */

	val = 0x0433;

	if (p == dsa_upstream_port(ds)) {

		val |= 0x0104;

		/* On 6085, unknown multicast forward is controlled

		 * here rather than in Port Control 2 register.

		 */

		if (ps->id == PORT_SWITCH_ID_6085)

			val |= 0x0008;

	}

	if (ds->dsa_port_mask & (1 << p))

		val |= 0x0100;

	REG_WRITE(addr, 0x04, val);



	/* Port Control 2: don't force a good FCS, don't use

	 * VLAN-based, source address-based or destination

	 * address-based priority overrides, don't let the switch

	 * add or strip 802.1q tags, don't discard tagged or

	 * untagged frames on this port, do a destination address

	 * lookup on received packets as usual, don't send a copy

	 * of all transmitted/received frames on this port to the

	 * CPU, and configure the upstream port number.

	 *

	 * If this is the upstream port for this switch, enable

	 * forwarding of unknown multicast addresses.

	 */

	if (ps->id == PORT_SWITCH_ID_6085)

		/* on 6085, bits 3:0 are reserved, bit 6 control ARP

		 * mirroring, and multicast forward is handled in

		 * Port Control register.

		 */

		REG_WRITE(addr, 0x08, 0x0080);

	else {

		val = 0x0080 | dsa_upstream_port(ds);

		if (p == dsa_upstream_port(ds))

			val |= 0x0040;

		REG_WRITE(addr, 0x08, val);

	}



	/* Rate Control: disable ingress rate limiting. */

	REG_WRITE(addr, 0x09, 0x0000);



	/* Rate Control 2: disable egress rate limiting. */

	REG_WRITE(addr, 0x0a, 0x0000);



	/* Port Association Vector: when learning source addresses

	 * of packets, add the address to the address database using

	 * a port bitmap that has only the bit for this port set and

	 * the other bits clear.

	 */

	REG_WRITE(addr, 0x0b, 1 << p);



	/* Tag Remap: use an identity 802.1p prio -> switch prio

	 * mapping.

	 */

	REG_WRITE(addr, 0x18, 0x3210);



	/* Tag Remap 2: use an identity 802.1p prio -> switch prio

	 * mapping.

	 */

	REG_WRITE(addr, 0x19, 0x7654);



	return mv88e6xxx_setup_port_common(ds, p);

}



static int mv88e6131_setup(struct dsa_switch *ds)

{

	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
@@ -251,14 +114,12 @@ static int mv88e6131_setup(struct dsa_switch *ds) 
	if (ret < 0)

		return ret;



	/* @@@ initialise vtu and atu */



	ret = mv88e6131_setup_global(ds);

	if (ret < 0)

		return ret;



	for (i = 0; i < ps->num_ports; i++) {

		ret = mv88e6131_setup_port(ds, i);

		ret = mv88e6xxx_setup_port(ds, i);

		if (ret < 0)

			return ret;

	}

drivers/net/dsa/mv88e6171.c

+5 −165
Original line number Diff line number Diff line
@@ -38,26 +38,17 @@ static char *mv88e6171_probe(struct device *host_dev, int sw_addr) 


static int mv88e6171_setup_global(struct dsa_switch *ds)

{

	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);

	int ret;

	int i;



	ret = mv88e6xxx_setup_global(ds);

	if (ret)

		return ret;



	/* Discard packets with excessive collisions, mask all

	 * interrupt sources, enable PPU.

	 */

	REG_WRITE(REG_GLOBAL, 0x04, 0x6000);



	/* Set the default address aging time to 5 minutes, and

	 * enable address learn messages to be sent to all message

	 * ports.

	 */

	REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);



	/* Configure the priority mapping registers. */

	ret = mv88e6xxx_config_prio(ds);

	if (ret < 0)

		return ret;



	/* Configure the upstream port, and configure the upstream

	 * port as the port to which ingress and egress monitor frames

	 * are to be sent.
@@ -72,158 +63,9 @@ static int mv88e6171_setup_global(struct dsa_switch *ds) 
	 */

	REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);



	/* Send all frames with destination addresses matching

	 * 01:80:c2:00:00:2x to the CPU port.

	 */

	REG_WRITE(REG_GLOBAL2, 0x02, 0xffff);



	/* Send all frames with destination addresses matching

	 * 01:80:c2:00:00:0x to the CPU port.

	 */

	REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);



	/* Disable the loopback filter, disable flow control

	 * messages, disable flood broadcast override, disable

	 * removing of provider tags, disable ATU age violation

	 * interrupts, disable tag flow control, force flow

	 * control priority to the highest, and send all special

	 * multicast frames to the CPU at the highest priority.

	 */

	REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);



	/* Program the DSA routing table. */

	for (i = 0; i < 32; i++) {

		int nexthop;



		nexthop = 0x1f;

		if (i != ds->index && i < ds->dst->pd->nr_chips)

			nexthop = ds->pd->rtable[i] & 0x1f;



		REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);

	}



	/* Clear all trunk masks. */

	for (i = 0; i < ps->num_ports; i++)

		REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0xff);



	/* Clear all trunk mappings. */

	for (i = 0; i < 16; i++)

		REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));



	/* Disable ingress rate limiting by resetting all ingress

	 * rate limit registers to their initial state.

	 */

	for (i = 0; i < 6; i++)

		REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8));



	/* Initialise cross-chip port VLAN table to reset defaults. */

	REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000);



	/* Clear the priority override table. */

	for (i = 0; i < 16; i++)

		REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8));



	/* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */



	return 0;

}



static int mv88e6171_setup_port(struct dsa_switch *ds, int p)

{

	int addr = REG_PORT(p);

	u16 val;



	/* MAC Forcing register: don't force link, speed, duplex

	 * or flow control state to any particular values on physical

	 * ports, but force the CPU port and all DSA ports to 1000 Mb/s

	 * full duplex.

	 */

	val = REG_READ(addr, 0x01);

	if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))

		REG_WRITE(addr, 0x01, val | 0x003e);

	else

		REG_WRITE(addr, 0x01, val | 0x0003);



	/* Do not limit the period of time that this port can be

	 * paused for by the remote end or the period of time that

	 * this port can pause the remote end.

	 */

	REG_WRITE(addr, 0x02, 0x0000);



	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,

	 * disable Header mode, enable IGMP/MLD snooping, disable VLAN

	 * tunneling, determine priority by looking at 802.1p and IP

	 * priority fields (IP prio has precedence), and set STP state

	 * to Forwarding.

	 *

	 * If this is the CPU link, use DSA or EDSA tagging depending

	 * on which tagging mode was configured.

	 *

	 * If this is a link to another switch, use DSA tagging mode.

	 *

	 * If this is the upstream port for this switch, enable

	 * forwarding of unknown unicasts and multicasts.

	 */

	val = 0x0433;

	if (dsa_is_cpu_port(ds, p)) {

		if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)

			val |= 0x3300;

		else

			val |= 0x0100;

	}

	if (ds->dsa_port_mask & (1 << p))

		val |= 0x0100;

	if (p == dsa_upstream_port(ds))

		val |= 0x000c;

	REG_WRITE(addr, 0x04, val);



	/* Port Control 2: don't force a good FCS, set the maximum

	 * frame size to 10240 bytes, don't let the switch add or

	 * strip 802.1q tags, don't discard tagged or untagged frames

	 * on this port, do a destination address lookup on all

	 * received packets as usual, disable ARP mirroring and don't

	 * send a copy of all transmitted/received frames on this port

	 * to the CPU.

	 */

	REG_WRITE(addr, 0x08, 0x2080);



	/* Egress rate control: disable egress rate control. */

	REG_WRITE(addr, 0x09, 0x0001);



	/* Egress rate control 2: disable egress rate control. */

	REG_WRITE(addr, 0x0a, 0x0000);



	/* Port Association Vector: when learning source addresses

	 * of packets, add the address to the address database using

	 * a port bitmap that has only the bit for this port set and

	 * the other bits clear.

	 */

	REG_WRITE(addr, 0x0b, 1 << p);



	/* Port ATU control: disable limiting the number of address

	 * database entries that this port is allowed to use.

	 */

	REG_WRITE(addr, 0x0c, 0x0000);



	/* Priority Override: disable DA, SA and VTU priority override. */

	REG_WRITE(addr, 0x0d, 0x0000);



	/* Port Ethertype: use the Ethertype DSA Ethertype value. */

	REG_WRITE(addr, 0x0f, ETH_P_EDSA);



	/* Tag Remap: use an identity 802.1p prio -> switch prio

	 * mapping.

	 */

	REG_WRITE(addr, 0x18, 0x3210);



	/* Tag Remap 2: use an identity 802.1p prio -> switch prio

	 * mapping.

	 */

	REG_WRITE(addr, 0x19, 0x7654);



	return mv88e6xxx_setup_port_common(ds, p);

}



static int mv88e6171_setup(struct dsa_switch *ds)

{

	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
@@ -240,8 +82,6 @@ static int mv88e6171_setup(struct dsa_switch *ds) 
	if (ret < 0)

		return ret;



	/* @@@ initialise vtu and atu */



	ret = mv88e6171_setup_global(ds);

	if (ret < 0)

		return ret;
@@ -250,7 +90,7 @@ static int mv88e6171_setup(struct dsa_switch *ds) 
		if (!(dsa_is_cpu_port(ds, i) || ds->phys_port_mask & (1 << i)))

			continue;



		ret = mv88e6171_setup_port(ds, i);

		ret = mv88e6xxx_setup_port(ds, i);

		if (ret < 0)

			return ret;

	}

drivers/net/dsa/mv88e6352.c

+5 −163
Original line number Diff line number Diff line
@@ -47,26 +47,17 @@ static char *mv88e6352_probe(struct device *host_dev, int sw_addr) 


static int mv88e6352_setup_global(struct dsa_switch *ds)

{

	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);

	int ret;

	int i;



	ret = mv88e6xxx_setup_global(ds);

	if (ret)

		return ret;



	/* Discard packets with excessive collisions,

	 * mask all interrupt sources, enable PPU (bit 14, undocumented).

	 */

	REG_WRITE(REG_GLOBAL, 0x04, 0x6000);



	/* Set the default address aging time to 5 minutes, and

	 * enable address learn messages to be sent to all message

	 * ports.

	 */

	REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);



	/* Configure the priority mapping registers. */

	ret = mv88e6xxx_config_prio(ds);

	if (ret < 0)

		return ret;



	/* Configure the upstream port, and configure the upstream

	 * port as the port to which ingress and egress monitor frames

	 * are to be sent.
@@ -78,156 +69,9 @@ static int mv88e6352_setup_global(struct dsa_switch *ds) 
	 */

	REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);



	/* Send all frames with destination addresses matching

	 * 01:80:c2:00:00:2x to the CPU port.

	 */

	REG_WRITE(REG_GLOBAL2, 0x02, 0xffff);



	/* Send all frames with destination addresses matching

	 * 01:80:c2:00:00:0x to the CPU port.

	 */

	REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);



	/* Disable the loopback filter, disable flow control

	 * messages, disable flood broadcast override, disable

	 * removing of provider tags, disable ATU age violation

	 * interrupts, disable tag flow control, force flow

	 * control priority to the highest, and send all special

	 * multicast frames to the CPU at the highest priority.

	 */

	REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);



	/* Program the DSA routing table. */

	for (i = 0; i < 32; i++) {

		int nexthop = 0x1f;



		if (i != ds->index && i < ds->dst->pd->nr_chips)

			nexthop = ds->pd->rtable[i] & 0x1f;



		REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);

	}



	/* Clear all trunk masks. */

	for (i = 0; i < 8; i++)

		REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7f);



	/* Clear all trunk mappings. */

	for (i = 0; i < 16; i++)

		REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));



	/* Disable ingress rate limiting by resetting all ingress

	 * rate limit registers to their initial state.

	 */

	for (i = 0; i < ps->num_ports; i++)

		REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8));



	/* Initialise cross-chip port VLAN table to reset defaults. */

	REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000);



	/* Clear the priority override table. */

	for (i = 0; i < 16; i++)

		REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8));



	/* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */



	return 0;

}



static int mv88e6352_setup_port(struct dsa_switch *ds, int p)

{

	int addr = REG_PORT(p);

	u16 val;



	/* MAC Forcing register: don't force link, speed, duplex

	 * or flow control state to any particular values on physical

	 * ports, but force the CPU port and all DSA ports to 1000 Mb/s

	 * full duplex.

	 */

	if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))

		REG_WRITE(addr, 0x01, 0x003e);

	else

		REG_WRITE(addr, 0x01, 0x0003);



	/* Do not limit the period of time that this port can be

	 * paused for by the remote end or the period of time that

	 * this port can pause the remote end.

	 */

	REG_WRITE(addr, 0x02, 0x0000);



	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,

	 * disable Header mode, enable IGMP/MLD snooping, disable VLAN

	 * tunneling, determine priority by looking at 802.1p and IP

	 * priority fields (IP prio has precedence), and set STP state

	 * to Forwarding.

	 *

	 * If this is the CPU link, use DSA or EDSA tagging depending

	 * on which tagging mode was configured.

	 *

	 * If this is a link to another switch, use DSA tagging mode.

	 *

	 * If this is the upstream port for this switch, enable

	 * forwarding of unknown unicasts and multicasts.

	 */

	val = 0x0433;

	if (dsa_is_cpu_port(ds, p)) {

		if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)

			val |= 0x3300;

		else

			val |= 0x0100;

	}

	if (ds->dsa_port_mask & (1 << p))

		val |= 0x0100;

	if (p == dsa_upstream_port(ds))

		val |= 0x000c;

	REG_WRITE(addr, 0x04, val);



	/* Port Control 2: don't force a good FCS, set the maximum

	 * frame size to 10240 bytes, don't let the switch add or

	 * strip 802.1q tags, don't discard tagged or untagged frames

	 * on this port, do a destination address lookup on all

	 * received packets as usual, disable ARP mirroring and don't

	 * send a copy of all transmitted/received frames on this port

	 * to the CPU.

	 */

	REG_WRITE(addr, 0x08, 0x2080);



	/* Egress rate control: disable egress rate control. */

	REG_WRITE(addr, 0x09, 0x0001);



	/* Egress rate control 2: disable egress rate control. */

	REG_WRITE(addr, 0x0a, 0x0000);



	/* Port Association Vector: when learning source addresses

	 * of packets, add the address to the address database using

	 * a port bitmap that has only the bit for this port set and

	 * the other bits clear.

	 */

	REG_WRITE(addr, 0x0b, 1 << p);



	/* Port ATU control: disable limiting the number of address

	 * database entries that this port is allowed to use.

	 */

	REG_WRITE(addr, 0x0c, 0x0000);



	/* Priority Override: disable DA, SA and VTU priority override. */

	REG_WRITE(addr, 0x0d, 0x0000);



	/* Port Ethertype: use the Ethertype DSA Ethertype value. */

	REG_WRITE(addr, 0x0f, ETH_P_EDSA);



	/* Tag Remap: use an identity 802.1p prio -> switch prio

	 * mapping.

	 */

	REG_WRITE(addr, 0x18, 0x3210);



	/* Tag Remap 2: use an identity 802.1p prio -> switch prio

	 * mapping.

	 */

	REG_WRITE(addr, 0x19, 0x7654);



	return mv88e6xxx_setup_port_common(ds, p);

}



#ifdef CONFIG_NET_DSA_HWMON



static int mv88e6352_get_temp(struct dsa_switch *ds, int *temp)
@@ -306,14 +150,12 @@ static int mv88e6352_setup(struct dsa_switch *ds) 
	if (ret < 0)

		return ret;



	/* @@@ initialise vtu and atu */



	ret = mv88e6352_setup_global(ds);

	if (ret < 0)

		return ret;



	for (i = 0; i < ps->num_ports; i++) {

		ret = mv88e6352_setup_port(ds, i);

		ret = mv88e6xxx_setup_port(ds, i);

		if (ret < 0)

			return ret;

	}

drivers/net/dsa/mv88e6xxx.c

+385 −20

File changed.

Preview size limit exceeded, changes collapsed.

CRA Git | Maintained and supported by SUSTech CRA and CCSE