Commit 54ce12e0 authored by Suravee Suthikulpanit's avatar Suravee Suthikulpanit Committed by Joerg Roedel
Browse files

iommu/amd: Re-purpose Exclusion range registers to support SNP CWWB 



When the IOMMU SNP support bit is set in the IOMMU Extended Features
register, hardware re-purposes the following registers:

1. IOMMU Exclusion Base register (MMIO offset 0020h) to
   Completion Wait Write-Back (CWWB) Base register

2. IOMMU Exclusion Range Limit (MMIO offset 0028h) to
   Completion Wait Write-Back (CWWB) Range Limit register

and requires the IOMMU CWWB semaphore base and range to be programmed
in the register offset 0020h and 0028h accordingly.

Signed-off-by: default avatarSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Link: https://lore.kernel.org/r/20200923121347.25365-4-suravee.suthikulpanit@amd.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 2818de6e

drivers/iommu/amd/amd_iommu_types.h

+1 −0
Original line number Diff line number Diff line
@@ -93,6 +93,7 @@ 
#define FEATURE_PC		(1ULL<<9)

#define FEATURE_GAM_VAPIC	(1ULL<<21)

#define FEATURE_EPHSUP		(1ULL<<50)

#define FEATURE_SNP		(1ULL<<63)



#define FEATURE_PASID_SHIFT	32

#define FEATURE_PASID_MASK	(0x1fULL << FEATURE_PASID_SHIFT)

drivers/iommu/amd/init.c

+26 −0
Original line number Diff line number Diff line
@@ -359,6 +359,29 @@ static void iommu_set_exclusion_range(struct amd_iommu *iommu) 
			&entry, sizeof(entry));

}



static void iommu_set_cwwb_range(struct amd_iommu *iommu)

{

	u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem);

	u64 entry = start & PM_ADDR_MASK;



	if (!iommu_feature(iommu, FEATURE_SNP))

		return;



	/* Note:

	 * Re-purpose Exclusion base/limit registers for Completion wait

	 * write-back base/limit.

	 */

	memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,

		    &entry, sizeof(entry));



	/* Note:

	 * Default to 4 Kbytes, which can be specified by setting base

	 * address equal to the limit address.

	 */

	memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,

		    &entry, sizeof(entry));

}



/* Programs the physical address of the device table into the IOMMU hardware */

static void iommu_set_device_table(struct amd_iommu *iommu)

{
@@ -1884,6 +1907,9 @@ static int __init amd_iommu_init_pci(void) 
		ret = iommu_init_pci(iommu);

		if (ret)

			break;



		/* Need to setup range after PCI init */

		iommu_set_cwwb_range(iommu);

	}



	/*

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