Commit 54b89756 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

Merge tag 'for-v3.13/cm-scm-cleanup-a' of... 

Merge tag 'for-v3.13/cm-scm-cleanup-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.13/cm-scm-cleanup

Move some of the OMAP2+ CM and System Control Module direct
register accesses into CM- and System Control
Module-specific "drivers" underneath arch/arm/mach-omap2/.  This
is a prerequisite for moving this code out of arch/arm/mach-omap2/ into
drivers/.

Basic test logs are available here:

http://www.pwsan.com/omap/testlogs/cm_scm_cleanup_a_v3.13/20131019101809/
parents d0e639c9 49e03402

arch/arm/mach-omap2/clkt2xxx_apll.c

+2 −2
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ static bool omap2xxx_clk_apll_locked(struct clk_hw *hw) 


	apll_mask = EN_APLL_LOCKED << clk->enable_bit;



	r = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);

	r = omap2xxx_cm_get_pll_status();



	return ((r & apll_mask) == apll_mask) ? true : false;

}
@@ -126,7 +126,7 @@ u32 omap2xxx_get_apll_clkin(void) 
{

	u32 aplls, srate = 0;



	aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);

	aplls = omap2xxx_cm_get_pll_config();

	aplls &= OMAP24XX_APLLS_CLKIN_MASK;

	aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;

arch/arm/mach-omap2/clkt2xxx_dpllcore.c

+4 −7
Original line number Diff line number Diff line
@@ -60,8 +60,7 @@ unsigned long omap2xxx_clk_get_core_rate(void) 


	core_clk = omap2_get_dpll_rate(dpll_core_ck);



	v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);

	v &= OMAP24XX_CORE_CLK_SRC_MASK;

	v = omap2xxx_cm_get_core_clk_src();



	if (v == CORE_CLK_SRC_32K)

		core_clk = 32768;
@@ -79,8 +78,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) 
{

	u32 high, low, core_clk_src;



	core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);

	core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;

	core_clk_src = omap2xxx_cm_get_core_clk_src();



	if (core_clk_src == CORE_CLK_SRC_DPLL) {	/* DPLL clockout */

		high = curr_prcm_set->dpll_speed * 2;
@@ -120,8 +118,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, 
	const struct dpll_data *dd;



	cur_rate = omap2xxx_clk_get_core_rate();

	mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);

	mult &= OMAP24XX_CORE_CLK_SRC_MASK;

	mult = omap2xxx_cm_get_core_clk_src();



	if ((rate == (cur_rate / 2)) && (mult == 2)) {

		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
@@ -145,7 +142,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, 
		tmpset.cm_clksel1_pll &= ~(dd->mult_mask |

					   dd->div1_mask);

		div = ((curr_prcm_set->xtal_speed / 1000000) - 1);

		tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);

		tmpset.cm_clksel2_pll = omap2xxx_cm_get_core_pll_config();

		tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;

		if (rate > low) {

			tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;

arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c

+6 −18
Original line number Diff line number Diff line
@@ -98,7 +98,7 @@ long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate, 
int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,

			    unsigned long parent_rate)

{

	u32 cur_rate, done_rate, bypass = 0, tmp;

	u32 cur_rate, done_rate, bypass = 0;

	const struct prcm_config *prcm;

	unsigned long found_speed = 0;

	unsigned long flags;
@@ -141,23 +141,11 @@ int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, 
		else

			done_rate = CORE_CLK_SRC_DPLL;



		/* MPU divider */

		omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);



		/* dsp + iva1 div(2420), iva2.1(2430) */

		omap2_cm_write_mod_reg(prcm->cm_clksel_dsp,

				 OMAP24XX_DSP_MOD, CM_CLKSEL);



		omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);



		/* Major subsystem dividers */

		tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;

		omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,

				 CM_CLKSEL1);



		if (cpu_is_omap2430())

			omap2_cm_write_mod_reg(prcm->cm_clksel_mdm,

					 OMAP2430_MDM_MOD, CM_CLKSEL);

		omap2xxx_cm_set_mod_dividers(prcm->cm_clksel_mpu,

					     prcm->cm_clksel_dsp,

					     prcm->cm_clksel_gfx,

					     prcm->cm_clksel1_core,

					     prcm->cm_clksel_mdm);



		/* x2 to enter omap2xxx_sdrc_init_params() */

		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);

arch/arm/mach-omap2/clock.c

+38 −0
Original line number Diff line number Diff line
@@ -542,6 +542,44 @@ int omap2_clk_disable_autoidle_all(void) 
	return 0;

}



/**

 * omap2_clk_deny_idle - disable autoidle on an OMAP clock

 * @clk: struct clk * to disable autoidle for

 *

 * Disable autoidle on an OMAP clock.

 */

int omap2_clk_deny_idle(struct clk *clk)

{

	struct clk_hw_omap *c;



	if (__clk_get_flags(clk) & CLK_IS_BASIC)

		return -EINVAL;



	c = to_clk_hw_omap(__clk_get_hw(clk));

	if (c->ops && c->ops->deny_idle)

		c->ops->deny_idle(c);

	return 0;

}



/**

 * omap2_clk_allow_idle - enable autoidle on an OMAP clock

 * @clk: struct clk * to enable autoidle for

 *

 * Enable autoidle on an OMAP clock.

 */

int omap2_clk_allow_idle(struct clk *clk)

{

	struct clk_hw_omap *c;



	if (__clk_get_flags(clk) & CLK_IS_BASIC)

		return -EINVAL;



	c = to_clk_hw_omap(__clk_get_hw(clk));

	if (c->ops && c->ops->allow_idle)

		c->ops->allow_idle(c);

	return 0;

}



/**

 * omap2_clk_enable_init_clocks - prepare & enable a list of clocks

 * @clk_names: ptr to an array of strings of clock names to enable

arch/arm/mach-omap2/clock.h

+2 −0
Original line number Diff line number Diff line
@@ -411,6 +411,8 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, 
void omap2_init_clk_hw_omap_clocks(struct clk *clk);

int omap2_clk_enable_autoidle_all(void);

int omap2_clk_disable_autoidle_all(void);

int omap2_clk_allow_idle(struct clk *clk);

int omap2_clk_deny_idle(struct clk *clk);

void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);

int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);

void omap2_clk_print_new_rates(const char *hfclkin_ck_name,

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