Merge branch 'omap-for-v5.6/ti-sysc-dt' into omap-for-v5.6/ti-sysc-drop-pdata (54a751f6) · Commits · 戴 / test

arch/arm/boot/dts/dra7.dtsi

+108 −32

Original line number	Diff line number	Diff line
		@@ -377,44 +377,120 @@
		ti,hwmods = "dmm";
		};

		mmu0_dsp1: mmu@40d01000 {
		target-module@40d01000 {
		compatible = "ti,sysc-omap2", "ti,sysc";
		reg = <0x40d01000 0x4>,
		<0x40d01010 0x4>,
		<0x40d01014 0x4>;
		reg-names = "rev", "sysc", "syss";
		ti,sysc-sidle = <SYSC_IDLE_FORCE>,
		<SYSC_IDLE_NO>,
		<SYSC_IDLE_SMART>;
		ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
		SYSC_OMAP2_SOFTRESET \|
		SYSC_OMAP2_AUTOIDLE)>;
		clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
		clock-names = "fck";
		resets = <&prm_dsp1 1>;
		reset-names = "rstctrl";
		ranges = <0x0 0x40d01000 0x1000>;
		#size-cells = <1>;
		#address-cells = <1>;

		mmu0_dsp1: mmu@0 {
		compatible = "ti,dra7-dsp-iommu";
		reg = <0x40d01000 0x100>;
		reg = <0x0 0x100>;
		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
		ti,hwmods = "mmu0_dsp1";
		#iommu-cells = <0>;
		ti,syscon-mmuconfig = <&dsp1_system 0x0>;
		status = "disabled";
		};
		};

		mmu1_dsp1: mmu@40d02000 {
		target-module@40d02000 {
		compatible = "ti,sysc-omap2", "ti,sysc";
		reg = <0x40d02000 0x4>,
		<0x40d02010 0x4>,
		<0x40d02014 0x4>;
		reg-names = "rev", "sysc", "syss";
		ti,sysc-sidle = <SYSC_IDLE_FORCE>,
		<SYSC_IDLE_NO>,
		<SYSC_IDLE_SMART>;
		ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
		SYSC_OMAP2_SOFTRESET \|
		SYSC_OMAP2_AUTOIDLE)>;
		clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
		clock-names = "fck";
		resets = <&prm_dsp1 1>;
		reset-names = "rstctrl";
		ranges = <0x0 0x40d02000 0x1000>;
		#size-cells = <1>;
		#address-cells = <1>;

		mmu1_dsp1: mmu@0 {
		compatible = "ti,dra7-dsp-iommu";
		reg = <0x40d02000 0x100>;
		reg = <0x0 0x100>;
		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
		ti,hwmods = "mmu1_dsp1";
		#iommu-cells = <0>;
		ti,syscon-mmuconfig = <&dsp1_system 0x1>;
		status = "disabled";
		};
		};

		mmu_ipu1: mmu@58882000 {
		target-module@58882000 {
		compatible = "ti,sysc-omap2", "ti,sysc";
		reg = <0x58882000 0x4>,
		<0x58882010 0x4>,
		<0x58882014 0x4>;
		reg-names = "rev", "sysc", "syss";
		ti,sysc-sidle = <SYSC_IDLE_FORCE>,
		<SYSC_IDLE_NO>,
		<SYSC_IDLE_SMART>;
		ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
		SYSC_OMAP2_SOFTRESET \|
		SYSC_OMAP2_AUTOIDLE)>;
		clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
		clock-names = "fck";
		resets = <&prm_ipu 2>;
		reset-names = "rstctrl";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x58882000 0x100>;

		mmu_ipu1: mmu@0 {
		compatible = "ti,dra7-iommu";
		reg = <0x58882000 0x100>;
		reg = <0x0 0x100>;
		interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
		ti,hwmods = "mmu_ipu1";
		#iommu-cells = <0>;
		ti,iommu-bus-err-back;
		status = "disabled";
		};
		};

		mmu_ipu2: mmu@55082000 {
		target-module@55082000 {
		compatible = "ti,sysc-omap2", "ti,sysc";
		reg = <0x55082000 0x4>,
		<0x55082010 0x4>,
		<0x55082014 0x4>;
		reg-names = "rev", "sysc", "syss";
		ti,sysc-sidle = <SYSC_IDLE_FORCE>,
		<SYSC_IDLE_NO>,
		<SYSC_IDLE_SMART>;
		ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
		SYSC_OMAP2_SOFTRESET \|
		SYSC_OMAP2_AUTOIDLE)>;
		clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
		clock-names = "fck";
		resets = <&prm_core 2>;
		reset-names = "rstctrl";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x55082000 0x100>;

		mmu_ipu2: mmu@0 {
		compatible = "ti,dra7-iommu";
		reg = <0x55082000 0x100>;
		reg = <0x0 0x100>;
		interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
		ti,hwmods = "mmu_ipu2";
		#iommu-cells = <0>;
		ti,iommu-bus-err-back;
		status = "disabled";
		};
		};

		abb_mpu: regulator-abb-mpu {

arch/arm/boot/dts/dra74x.dtsi

+55 −16

Original line number	Diff line number	Diff line
		@@ -66,24 +66,63 @@
		};
		};

		mmu0_dsp2: mmu@41501000 {
		target-module@41501000 {
		compatible = "ti,sysc-omap2", "ti,sysc";
		reg = <0x41501000 0x4>,
		<0x41501010 0x4>,
		<0x41501014 0x4>;
		reg-names = "rev", "sysc", "syss";
		ti,sysc-sidle = <SYSC_IDLE_FORCE>,
		<SYSC_IDLE_NO>,
		<SYSC_IDLE_SMART>;
		ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
		SYSC_OMAP2_SOFTRESET \|
		SYSC_OMAP2_AUTOIDLE)>;
		clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
		clock-names = "fck";
		resets = <&prm_dsp2 1>;
		reset-names = "rstctrl";
		ranges = <0x0 0x41501000 0x1000>;
		#size-cells = <1>;
		#address-cells = <1>;

		mmu0_dsp2: mmu@0 {
		compatible = "ti,dra7-dsp-iommu";
		reg = <0x41501000 0x100>;
		reg = <0x0 0x100>;
		interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
		ti,hwmods = "mmu0_dsp2";
		#iommu-cells = <0>;
		ti,syscon-mmuconfig = <&dsp2_system 0x0>;
		status = "disabled";
		};
		};

		mmu1_dsp2: mmu@41502000 {
		target-module@41502000 {
		compatible = "ti,sysc-omap2", "ti,sysc";
		reg = <0x41502000 0x4>,
		<0x41502010 0x4>,
		<0x41502014 0x4>;
		reg-names = "rev", "sysc", "syss";
		ti,sysc-sidle = <SYSC_IDLE_FORCE>,
		<SYSC_IDLE_NO>,
		<SYSC_IDLE_SMART>;
		ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
		SYSC_OMAP2_SOFTRESET \|
		SYSC_OMAP2_AUTOIDLE)>;

		clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
		clock-names = "fck";
		resets = <&prm_dsp2 1>;
		reset-names = "rstctrl";
		ranges = <0x0 0x41502000 0x1000>;
		#size-cells = <1>;
		#address-cells = <1>;

		mmu1_dsp2: mmu@0 {
		compatible = "ti,dra7-dsp-iommu";
		reg = <0x41502000 0x100>;
		reg = <0x0 0x100>;
		interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
		ti,hwmods = "mmu1_dsp2";
		#iommu-cells = <0>;
		ti,syscon-mmuconfig = <&dsp2_system 0x1>;
		status = "disabled";
		};
		};
		};
		};

arch/arm/boot/dts/omap4-l4.dtsi

+8 −3

Original line number	Diff line number	Diff line
		@@ -320,7 +320,6 @@

		target-module@66000 { /* 0x4a066000, ap 25 26.0 */
		compatible = "ti,sysc-omap2", "ti,sysc";
		ti,hwmods = "mmu_dsp";
		reg = <0x66000 0x4>,
		<0x66010 0x4>,
		<0x66014 0x4>;
		@@ -334,12 +333,18 @@
		/* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */
		clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
		clock-names = "fck";
		resets = <&prm_tesla 1>;
		reset-names = "rstctrl";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x66000 0x1000>;

		/* mmu_dsp cannot be moved before reset driver */
		status = "disabled";
		mmu_dsp: mmu@0 {
		compatible = "ti,omap4-iommu";
		reg = <0x0 0x100>;
		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <0>;
		};
		};
		};

arch/arm/boot/dts/omap4.dtsi

+28 −15

Original line number	Diff line number	Diff line
		@@ -173,14 +173,6 @@
		#gpio-cells = <2>;
		};

		mmu_dsp: mmu@4a066000 {
		compatible = "ti,omap4-iommu";
		reg = <0x4a066000 0x100>;
		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
		ti,hwmods = "mmu_dsp";
		#iommu-cells = <0>;
		};

		target-module@52000000 {
		compatible = "ti,sysc-omap4", "ti,sysc";
		ti,hwmods = "iss";
		@@ -206,14 +198,35 @@
		/* No child device binding, driver in staging */
		};

		mmu_ipu: mmu@55082000 {
		target-module@55082000 {
		compatible = "ti,sysc-omap2", "ti,sysc";
		reg = <0x55082000 0x4>,
		<0x55082010 0x4>,
		<0x55082014 0x4>;
		reg-names = "rev", "sysc", "syss";
		ti,sysc-sidle = <SYSC_IDLE_FORCE>,
		<SYSC_IDLE_NO>,
		<SYSC_IDLE_SMART>;
		ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
		SYSC_OMAP2_SOFTRESET \|
		SYSC_OMAP2_AUTOIDLE)>;
		clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
		clock-names = "fck";
		resets = <&prm_core 2>;
		reset-names = "rstctrl";
		ranges = <0x0 0x55082000 0x100>;
		#size-cells = <1>;
		#address-cells = <1>;

		mmu_ipu: mmu@0 {
		compatible = "ti,omap4-iommu";
		reg = <0x55082000 0x100>;
		reg = <0x0 0x100>;
		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
		ti,hwmods = "mmu_ipu";
		#iommu-cells = <0>;
		ti,iommu-bus-err-back;
		};
		};

		target-module@4012c000 {
		compatible = "ti,sysc-omap4", "ti,sysc";
		reg = <0x4012c000 0x4>,

arch/arm/boot/dts/omap5-l4.dtsi

+8 −3

Original line number	Diff line number	Diff line
		@@ -349,7 +349,6 @@

		target-module@66000 { /* 0x4a066000, ap 23 0a.0 */
		compatible = "ti,sysc-omap2", "ti,sysc";
		ti,hwmods = "mmu_dsp";
		reg = <0x66000 0x4>,
		<0x66010 0x4>,
		<0x66014 0x4>;
		@@ -364,12 +363,18 @@
		/* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */
		clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
		clock-names = "fck";
		resets = <&prm_dsp 1>;
		reset-names = "rstctrl";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x66000 0x1000>;

		/* mmu_dsp cannot be moved before reset driver */
		status = "disabled";
		mmu_dsp: mmu@0 {
		compatible = "ti,omap4-iommu";
		reg = <0x0 0x100>;
		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <0>;
		};
		};

		target-module@70000 { /* 0x4a070000, ap 79 2e.0 */

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